hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 56

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
3. Truth Tables
(Extended) Mode Register Set
Refresh (REF)
Self Refresh Entry
Self Refresh Exit
Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto-Precharge
No Operation
Device Deselect
Power Down Entry
Power Down Exit
1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addesses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
3.1 Command truth table.
Register.
rupted by a Write" in section 2.2.4 for details.
requirements outlined in section 2.2.7.
section 2.2.2.4.
Function
Previous
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Current
Cycle
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
H
H
X
H
X
X
X
L
L
L
L
L
L
CAS
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
WE
H
H
H
H
H
H
H
H
H
L
X
L
L
L
L
X
X
X
BA0
BA1
BA2
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
1HY5PS12421(L)M
A15-A11
Column
Column
Column
Column
HY5PS12821(L)M
X
X
X
X
X
X
X
X
X
Row Address
OP Code
A10
X
X
X
H
H
H
X
X
X
X
L
L
L
Column
Column
Column
Column
A9 - A0
X
X
X
X
X
X
X
X
X
Notes
1,2,3,
1,2,3,
1,2,3
1,2,3
56
1,2
1,7
1,2
1,2
1,4
1,4
1
1
1
1
1