r6781-12 Conexant Systems, Inc., r6781-12 Datasheet - Page 43

• Manufacturer Part Number: r6781-12
• Description: Embedded Modem Family
• Manufacturer: Conexant Systems, Inc.

EmbeddedModem Family
Table 3-5. Hardware Interface Signal Definitions (3 of 5)
D224ATLVDSC
DCDL
DTRL
HA0-HA2
HD0-HD7
HCS
HRD
HWT
Label
DO
DO
DI
DIO
DI
DI
DI
I/O Type
DCD Indicator. The DCDL output is controlled by the AT&C command.
DTR Indicator. The DTRL output is controlled by the AT&D command.
When the HWT input signal is connected to the host bus write line, the parallel interface is
selected upon reset. (See
timing information.)
Registers). Parallel interface operation is equivalent to 16C450 operation with CS0 and CS1
inputs high and DISTR, DOSTR, and ADS inputs low. The corresponding RC224ATLV and
16C450 signals are shown below. 16C450 signals that are not required for RC224ATLV host
computer operation are not shown.
Host Bus Address Lines 0-2. During a host read or write operation, signals HA0–HA2 select
an internal register. The state of the divisor latch access bit (DLAB) affects the selection of
certain registers.
Host Bus Data Lines 0-7. HD0-HD7 are comprised of eight tri-state I/O lines providing
bidirectional communication between the host and the modem. Data, control words, and
status information are transferred through HD0-HD7.
Host Bus Chip Select. HCS input low enables reading from or writing to the modem using the
parallel bus.
Host Bus Read. HRD is an active low read control input. When the modem is selected with
HCS, HRD low allows status or data words to be read from an addressed register.
Host Bus Write. HWT is an active low write control input. When the modem is selected with
HCS, HWT low allows data or control words to be written to an addressed register.
16C450 Signal
DLAB
0
0
X
X
X
X
X
1
1
Parallel Host Interface (Parallel Interface Only)
The parallel interface emulates a 16C450 UART; (See
A0 - A2
D0 - D7
MR
CS2
DISTR
DOSTR
INTRPT
DDIS
OUT2
HA2
0
0
0
0
1
1
1
0
0
HA1
0
0
1
1
0
0
1
0
0
Conexant
Section 7.3, Interface Timing and Waveforms
RC224ATLV Signal
HA0
0
1
0
1
0
1
1
0
1
Signal Name/Description
HA0 - HA2
HD0 - HD7
RESET (Active low)
HCS
HWT
HINT
HDIS
None (Implemented internally in RC224ATLV)
HRD
Line Status Register (Read Only)
Receive Buffer Register (Read),
Transmitter Holding Register (Write)
Interrupt Enable Register
Interrupt Identification Register (Read Only)
Line Control Register
Modem Control Register
Scratch Register
Divisor Latch Register (Least Significant Byte)
Divisor Latch Register (Most Significant Byte)
Table 2-1, Parallel Interface
Register
for waveform and
3-17