r6781-12 Conexant Systems, Inc., r6781-12 Datasheet - Page 25

• Manufacturer Part Number: r6781-12
• Description: Embedded Modem Family
• Manufacturer: Conexant Systems, Inc.

EmbeddedModem Family
D224ATLVDSC
Receiver Buffer Register
Modem Status Register
DCD
Transmitter Holding
7
(Addr=0, DLAB=0)
Register (Addr=0,
(Addr = 6)
DLAB=0)
RI
6
The Modem Status Register (MSR) reports the modem’s current state and change
information. Bits 4-7 supply current state, and bits 0-3 supply change
information. The change bits are set to a logic 1 whenever a control input from the
modem changes state from the last MSR read by the host. Bits 0-3 are reset to
logic 0 when the host reads the MSR or upon reset.
generated.
DCD
RI
DSR
CTS
DDCD
TERI
DDSR
DCTS
The Receiver Buffer Register (RBR) is a read-only register at location 0 (with
DLAB = 0). Bit 0 is the least significant bit of the data, and is the first bit
received.
The Transmitter Holding Register (THR) is a write-only register at address 0
when DLAB = 0. Bit 0 is the least significant bit and the first bit sent.
DSR
Whenever Bits 0,1, 2, or 3 are set to a logic 1, a Modem Status Interrupt is
5
CTS
4
Data Carrier Detect. This bit indicates the logic state of the
DCD output. If Loopback is selected (MCR4 = 1), this bit
reflects the state of OUT2 in the MCR (MCR3).
Ring Indicator. This bit indicates the logic state of the RI
output. If Loopback is selected (MCR4 = 1), this bit reflects
the state of OUT1 in the MCR (MCR2).
Data Set Ready. This bit indicates the logic state of the DSR
output. If Loopback is selected (MCR4 = 1), this bit reflects
the state of DTR in the MCR (MCR0).
Clear to Send. This bit indicates the logic state of the CTS
output. If Loopback is selected (MCR4 = 1), this bit reflects
the state of RTS in the MCR (MCR1).
Delta Data Carrier Detect. This bit is set to a logic 1 when
the DCD bit has changed since the MSR was last read by the
host.
Trailing Edge of Ring Indicator. This bit is set to a logic 1
when the RI bit changes from a 1 to a 0 state since the MSR
was last read by the host.
Delta Data Set Ready. This bit is set to a logic I when the
DSR bit has changed state since the MSR was last read by the
host.
Delta Clear to Send. This bit is set to a logic 1 when the CTS
bit has changed state since the MSR was last read by the host.
Conexant
DDCD
3
TERI
2
DDSR
1
2.1 Hardware Interface
DCTS
0
2-11