bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 127

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.2 Global Control and Status Registers
Unused bits indicated by a dash (
effect.
Read only value.
DID[7:4]
DID[3:0]
RESET
N8370DSE
000— Device Identification (DID)
001— Primary Control Register (CR0)
DID[7]
RESET
7
7
Device ID—A value of 0x0 indicates Bt8370.
A value of 0x5 indicates the Bt8375.
A value of 0x6 indicates the Bt8376.
Device Revision—A value of 0x8 indicates the current revision. Prior revisions are obsolete.
Device Reset—Active-high indicates a device reset is in progress. The device reset is initiated
by a power-on reset, a software reset, or a hardware reset (RST* pin is active low). RESET can
be monitored to determine when the reset process is complete.
6
and causes the Bt8370/8375/8376 to initialize certain control registers to their default settings,
as shown in
RESET returns low, although other non-default registers can be processor-initialized while
RESET is active.
system can three-state the transmit line driver by holding the XOE pin inactive (low).
DID[6]
µ
—
To initiate a software reset, the processor must first write RESET to 0, then delay at least
To avoid non-compliant line rate or pulse shape transmissions during the reset process, the
After the reset process, the following is true:
s, then write RESET to 1. Once initiated, the reset process continues for 15
6
6
Table 3-1, Address
DID[5]
—
1.
2.
3.
4.
—
5
5
) are reserved and should be written to 0. Writing to reserved bits has no
System bus outputs RSIGO, RPCMO, and SIGFRZO are three-stated.
Interrupt INTR* output is disabled.
Programmable I/O pins are configured as inputs: RFSYNC, RMSYNC,
TFSYNC, TMSYNC, TNEGI/TDLCLKO, and ONESEC.
CONEXANT production test modes are disabled.
RFRAME[3]
DID[4]
4
4
Map. The processor must not write to these registers until
Conexant
RFRAME[2]
DID[3]
3
3
RFRAME[1]
DID[2]
2
2
3.2 Global Control and Status Registers
RFRAME[0]
DID[1]
1
1
µ
s maximum,
3.0 Registers
T1/E1N
DID[0]
0
0
3-9