SST25VF040B-50-4I-SAE SST [Silicon Storage Technology, Inc], SST25VF040B-50-4I-SAE Datasheet - Page 9

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SST25VF040B-50-4I-SAE

Manufacturer Part Number
SST25VF040B-50-4I-SAE
Description
4 Mbit SPI Serial Flash
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet

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4 Mbit SPI Serial Flash
SST25VF040B
Read (25/33 MHz)
The Read instruction, 03H, supports up to 25 MHz (for
SST25VF040B-50-xx-xxF) or 33 MHz (for SST25VF040B-
80-xx-xxE) Read. The device outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
©2009 Silicon Storage Technology, Inc.
FIGURE 5: Read Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0 1 2 3 4 5 6 7 8
03
HIGH IMPEDANCE
MSB
ADD.
15 16
ADD.
23 24
9
ADD.
beginning (wrap-around) of the address space. Once the
data from address location 1FFFFFH has been read, the
next output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
remain active low for the duration of the Read cycle. See
Figure 5 for the Read sequence.
MSB
31 32
D
OUT
N
39 40
D
N+1
OUT
47 48
D
N+2
OUT
55 56
D
N+3
OUT
63 64
D
1295 ReadSeq.0
N+4
S71295-05-000
OUT
23
-A
70
0
]. CE# must
Data Sheet
10/09

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