SST25VF040B-50-4I-SAE SST [Silicon Storage Technology, Inc], SST25VF040B-50-4I-SAE Datasheet - Page 10

• Manufacturer Part Number: SST25VF040B-50-4I-SAE
• Description: 4 Mbit SPI Serial Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
High-Speed-Read (50/80 MHz)
The High-Speed-Read instruction supporting up to 50 MHz
(for
SST25VF040B-80-xx-xxE) Read is initiated by executing
an 8-bit command, 0BH, followed by address bits [A
and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 6 for
the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruc-
tion outputs the data starting from the specified address
location. The data output stream is continuous through all
©2009 Silicon Storage Technology, Inc.
SCK
CE#
FIGURE 6: High-Speed-Read Sequence
SO
SI
SST25VF040B-50-xx-xxF)
MODE 3
MODE 0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
MSB
0 1 2 3 4 5 6 7 8
0B
HIGH IMPEDANCE
or
MSB
80
ADD.
15 16
MHz
ADD.
23
-A
23 24
(for
0
]
ADD.
10
IL
or V
31 32
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. Once the data from address
location 7FFFFH has been read, the next output will be
from address location 00000H.
IH
)
X
39 40
MSB
D
OUT
N
47 48
D
N+1
OUT
4 Mbit SPI Serial Flash
55 56
D
N+2
OUT
63 64
SST25VF040B
D
N+3
OUT
S71295-05-000
71 72
1295 HSRdSeq.0
D
N+4
OUT
80
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