SST25VF040B-50-4I-SAE SST [Silicon Storage Technology, Inc], SST25VF040B-50-4I-SAE Datasheet - Page 15

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SST25VF040B-50-4I-SAE

Manufacturer Part Number
SST25VF040B-50-4I-SAE
Description
4 Mbit SPI Serial Flash
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet

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4 Mbit SPI Serial Flash
SST25VF040B
4-KByte Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Sector-Erase instruction is
initiated by executing an 8-bit command, 20H, followed by
address bits [A
©2009 Silicon Storage Technology, Inc.
FIGURE 12: Sector-Erase Sequence
23
-A
0
]. Address bits [A
SCK
CE#
SO
SI
MODE 3
MODE 0
MS
-A
12
] (A
MSB
0 1 2 3 4 5 6 7 8
MS
= Most
20
HIGH IMPEDANCE
15
MSB
Significant address) are used to determine the sector
address (SA
CE# must be driven high before the instruction is executed.
The user may poll the Busy bit in the software status regis-
ter or wait T
Sector-Erase cycle. See Figure 12 for the Sector-Erase
sequence.
ADD.
15 16
ADD.
SE
X
), remaining address bits can be V
23 24
for the completion of the internal self-timed
1295 SecErase.0
ADD.
31
S71295-05-000
Data Sheet
IL
or V
10/09
IH.

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