IDT7187L25DB IDT [Integrated Device Technology], IDT7187L25DB Datasheet - Page 7

• Manufacturer Part Number: IDT7187L25DB
• Description: CMOS STATIC RAM 64K (64K x 1-BIT)
• Manufacturer: IDT [Integrated Device Technology]

IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
DATA
NOTES:
1.
2. A write occurs during the overlap (t
3. t
4. If the
5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig).
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
NOTES:
1.
2. A write occurs during the overlap (t
3. t
4. If the
5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig).
ADDRESS
ADDRESS
DATA
WE
DATA
WE
WR
WR
OUT
or
is measured from the earlier of
or
is measured from the earlier of
CS
WE
CS
CS
WE
CS
IN
CS
CS
IN
LOW transition occurs simultaneously with or after the
LOW transition occurs simultaneously with or after the
must be HIGH during all address transitions.
must be HIGH during all address transitions.
t
t
AS
AS
WP
WP
CS
CS
) of a LOW
) of a LOW
or
or
WE
WE
going HIGH to the end of the write cycle.
going HIGH to the end of the write cycle.
CS
CS
t
WZ
and a LOW
and a LOW
(5)
t
t
AW
AW
WE
WE
WE
WE
LOW transition, the outputs remain in the high-impedance state.
LOW transition, the outputs remain in the high-impedance state.
.
.
t
t
t
t
WC
WP
CW
WC
6.2
WE WE
CS CS
CONTROLLED TIMING)
CONTROLLED TIMING)
t
DW
t
VALID DATA
DW
VALID DATA
t
t
DH
WR
t
t
WR
t
OW
t
(3)
DH
MILITARY TEMPERATURE RANGE
(5)
(1,2,4)
(1,2,3,4)
2986 drw 09
2986 drw 10
7