IDT7187L25DB IDT [Integrated Device Technology], IDT7187L25DB Datasheet - Page 6

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IDT7187L25DB

Manufacturer Part Number
IDT7187L25DB
Description
CMOS STATIC RAM 64K (64K x 1-BIT)
Manufacturer
IDT [Integrated Device Technology]
Datasheet

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IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1
TIMING WAVEFORM OF READ CYCLE NO. 2
NOTES:
1.
2.
3. Address valid prior to or coincident with
4. Transition is measured 200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
AC ELECTRICAL CHARACTERISTICS
NOTES:
1. –55 C to +125 C temperature range only.
2. This parameter guaranteed but not tested.
DATA
CURRENT
Symbol
ADDRESS
Write Cycle
t
t
t
t
t
t
t
t
t
t
WC
CW
AW
AS
WP
WR
DW
DH
WZ
OW
SUPPLY
WE
CS
(2)
(2)
is LOW for Read cycle.
OUT
is HIGH for Read cycle.
DATA
V
CC
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Write Enable to Output in High-Z
Output Active from End-of-Write
OUT
CS
I
I
CC
SB
Parameter
PREVIOUS DATA VALID
CS
transition LOW.
t
OH
t
PU
t
t
AA
LZ
(V
(4)
CC
= 5.0V
(1,2)
(1,3)
t
ACS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
20
20
20
15
7187S25
0
0
5
0
7187L25
6.2
10%, All Temperature Ranges)
12
— 35/45
— 25/40
— 25/40
— 20/25
— 15/25
t
t
RC
RC (5)
7187S35/45
7187L35/45
(5)
0
0
5
0
15/30 —
(1)
(1)
7187S55
7187L55
55
50
50
35
25
0
0
5
0
DATA VALID
30
(1)
(1)
DATA VALID
MILITARY TEMPERATURE RANGE
7187S70
7187L70
70
55
55
40
30
0
0
5
0
30
(1)
t
(1)
HZ
t
PD
(4)
7187S85
7187L85
85
65
65
45
35
0
0
5
0
IMPEDANCE
40
(1)
(1)
HIGH
2986 drw 07
2986 drw 08
2986 tbl 12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6

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