ADF4116 Analog Devices, ADF4116 Datasheet - Page 19

• Manufacturer Part Number: ADF4116
• Description: Single, Integer-n 550 MHZ PLL
• Manufacturer: Analog Devices

INTERFACING
The ADF4116 family has a simple SPI-compatible serial inter-
face for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
OSC 3B1-13M0
MODULATED
TCXO
FREF
NTERFACE
DIGITAL
DIGITAL
DATA
SERIAL
IN
100pF
2k
REF
REFIO
FS ADJ
RF
AD9761
T
X
IN
IN
ADF4118
8
DAC
B
0.1 F
R
AV
REF
7
SET
V
3
DD
DD
QOUTA
QOUTB
RF
ADF4116/
ADF4117/
IOUTA
IOUTB
IN
ADF4118
15
IN
4
DV
A
51
CP
100pF
DD
16
9
680pF
V
V
RF
RF
FL
P
P
POWER-DOWN CONTROL
IN
IN
CE
CP
O
A
B
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS
ARE OMITTED FROM DIAGRAM FOR CLARITY.
2
1
6
5
100pF
LOW-PASS
LOW-PASS
10k
100pF
FILTER
FILTER
1k
6.8nF
10k
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
18pF
51
FILTER
LOOP
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems that will have typical lock times in hun-
dreds of microseconds.
VCO190-1960T
100pF
100pF
GND
ADF4116/ADF4117/ADF4118
V
IBBP
IBBP
QBBP
QBBP
IN
LOIN
D
CC
S
ADG702
VCO
18
GND
V
AD8346
18
DD
100pF
18
100pF
VOUT
LOIP
100pF
18
100pF
18
18
RF
OUT
RF
OUT