ADF4116 Analog Devices, ADF4116 Datasheet - Page 11

• Manufacturer Part Number: ADF4116
• Description: Single, Integer-n 550 MHZ PLL
• Manufacturer: Analog Devices

INPUT SHIFT REGISTER
The ADF4116 family digital section includes a 21-bit input
shift register, a 14-bit R counter and an 18-bit N counter,
comprising a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 21-bit shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred
from the shift register to one of four latches on the rising edge
of LE. The destination latch is determined by the state of the
two control bits (C2, C1) in the shift register. These are the
two LSBs DB1, DB0 as shown in the timing diagram of Fig-
ure 1. The truth table for these bits is shown in Table VI.
Table I shows a summary of how the latches are programmed.
DB20
DB20
DB20
DB20
LDP
G1
X
X
DB19
DB19
DB19
DB19
PD2
PD2
B13
T4
DB18
DB18
DB18
DB18
B12
MODE BITS
T3
X
X
TEST
RESERVED
RESERVED
DB17
DB17
B11
DB17
DB17
T2
X
X
DB16
DB16
DB16
DB16
B10
T1
X
X
DB15
DB15
DB15
DB15
R14
TC4
TC4
B9
TIMER COUNTER
TIMER COUNTER
DB14
DB14
DB14
DB14
R13
TC3
TC3
B8
13-BIT B COUNTER
CONTROL
CONTROL
Table II. ADF4116 Family Latch Summary
DB13
DB13
DB13
DB13
R12
TC2
TC2
B7
REFERENCE COUNTER LATCH
DB12
DB12
DB12
R11
DB12
TC1
B6
TC1
INITIALIZATION LATCH
AB COUNTER LATCH
FUNCTION LATCH
DB11
DB11
DB11
DB11
R10
B5
F6
F6
14-BIT REFERENCE COUNTER, R
DB10
DB10
DB10
DB10
R9
B4
X
X
DB9
DB9
DB9
DB9
R8
B3
F4
F4
DB8
DB8
DB8
DB8
C2
0
0
1
1
R7
B2
F3
F3
Control Bits
DB7
DB7
DB7
DB7
ADF4116/ADF4117/ADF4118
R6
B1
F2
F2
Table I. C2, C1 Truth Table
C1
0
1
0
1
DB6
DB6
DB6
DB6
R5
A5
M3
M3
CONTROL
CONTROL
MUXOUT
MUXOUT
DB5
DB5
DB5
DB5
R4
A4
M2
M2
5-BIT A COUNTER
Data Latch
R Counter
N Counter (A and B)
Function Latch
Initialization Latch
DB4
DB4
DB4
R3
A3
DB4
M1
M1
DB3
DB3
DB3
PD1
PD1
DB3
R2
A2
DB2
DB2
DB2
DB2
R1
A1
F1
F1
C2 (0)
C2 (0)
C2 (1)
C2 (1)
DB1
DB1
DB1
DB1
CONTROL
CONTROL
CONTROL
CONTROL
BITS
BITS
BITS
BITS
C1 (0)
C1 (1)
C1 (0)
C1 (1)
DB0
DB0
DB0
DB0