MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 54

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Physical and Electrical Specifications
2.6.5
2.6.5.1 Core Data Transfers
Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock
(REFCLK), which is
Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of DLLIN (and
T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-15 shows.
Figure 2-9 is a graphical representation of Table 2-15.
Note: The UPM machine and GPCM machine outputs change on the internal tick determined by the memory
2-14
1:2, 1:3, 1:4, 1:5, 1:6
controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs
change only on the
PLL Clock Ratio
System Bus Access Timing
1:2.5
1:3.5
DLLIN
DLLIN
DLLIN
DLLIN
Figure 2-9.
T1
T1
T1
. Memory controller signals, however, trigger on four points within a DLLIN cycle.
DLLIN
Table 2-15.
MSC8103 Network Digital Signal Processor, Rev. 11
rising edge.
T2
T2
Internal Tick Spacing for Memory Controller Signals
T2
3/10 DLLIN
4/14 DLLIN
1/4 DLLIN
Tick Spacing for Memory Controller Signals
T2
T3
T3
T3
Tick Spacing (T1 Occurs at the Rising Edge of DLLIN)
T4
T4
T4
1/2 DLLIN
1/2 DLLIN
1/2 DLLIN
T3
for 1:2, 1:3, 1:4, 1:5, 1:6
for 1:2.5
for 1:3.5
Freescale Semiconductor
11/14 DLLIN
8/10 DLLIN
3/4 DLLIN
T4