MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 101

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus
frequency (that is, 25 MHz).
For the same reason the data pins frequency is 3.125 MHz.
Calculating internal power (from Table 2-5 values):
Maximum allowed ambient temperature is:
4.4 Layout Practices
Each
Similarly, each
distinct groups of logic on the chip. The
by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip
capacitor lead. A four-layer board is recommended, employing two inner layers as
All output pins on the MSC8103 have fast rise and fall times. Printed circuit board (PCB) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output switching
times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six
inches are recommended. Capacitance calculations should consider all device loads as well as parasitic
capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in
systems with higher capacitive loads because these loads create higher transient currents in the
circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to
minimize the noise levels on the PLL supply pins.
There are 2 pairs of PLL supply pins:
ensure internal clock stability, filter the power to the
Figure 4-2. To filter as much noise as possible, place the circuit as close as possible to
0.01-µF capacitor should be closest to
and finally the 10-Ω resistor to
Freescale Semiconductor
P
P
P
P
P
T
Data, HRD, HRW
A
CORE
CPM
SIU
INT
D
V
CC
= P
= T
Total P
CLKOUT
Address
(50) = ((P
= P
Pins
and
(100) = ((P
INT
J
(200) = ((P
– (PD × θ
CORE
I/O
V
+ P
DD
GND
(200) + P
pin on the MSC8103 should be provided with a low-impedance path to the board’s power supply.
I/O
SIU
pin should be provided with a low-impedance path to ground. The power supply pins drive
CPM
= 505 + 67 = 572
CORE
– P
JA
Number of Pins
)
– P
LSI
Switching
CPM
– P
) / 100) × 50 + P
LCP
V
34
LCO
(100) + P
4
1
MSC8103 Network Digital Signal Processor, Rev. 11
DD
) / 200) × 100 + P
. These traces should be kept short and direct.
)/300) × 200 + P
V
V
CCSYN
CCSYN
V
SIU
Table 4-1.
CC
(50) = 301 + 163 + 41 = 505
power supply should be bypassed to ground using at least four 0.1 µF
-
GND
LSI
and
× 30
× 30
× 30
× C
= ((80 – 2) / 100) × 50 + 2 = 41
SYN
V
V
LCP
CCSYN1
CC
LCO
V
CCSYN
and
,
Power Dissipation
= ((320 – 6) / 200) × 100 + 6 = 163
V
=((450 – 3) / 300 × 200 + 3 = 301
DD
, followed by the 10-µF capacitor, the 10-nH inductor,
V
, and
CCSYN1
and
V
× V
GND
CCSYN1
× 3.3
× 3.3
× 3.3
-
GND
DDH
should be kept to less than half an inch per
2
2
2
2
SYN1
inputs with a circuit similar to the one in
. Each pair supplies one PLL. To
× 3. 125 × 10
× 12.5 × 10
× 50 × 10
× f × 10
V
CC
V
and
CCSYN
–3
–3
–3
GND
–3
and
V
CC
planes.
Layout Practices
,
V
Power in mW
V
CCSYN1
DD
16.25
34.75
, and
16
67
. The
GND
4-3