MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 50

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Physical and Electrical Specifications
2.6.4.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic
modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized
only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The
MSC8103 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration, and
reduced reset configuration.
2.6.4.2 Power-On Reset Flow
Asserting the
least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 V
MSC8103 has five configuration pins, four of which are multiplexed with the SC140 EONCE Event (
EE[4–5]
addition to these configuration pins, three (
pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by
defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies.
2-10
RSTCONF
DBREQ/ EE0
HPE/EE1
BTM[0–1]/
EE[4–5]
No.
1
2
3
Pin
) pins and the fifth of which is the
Required external PORESET duration minimum
•
•
Delay from deassertion of external PORESET to deassertion of
internal PORESET
•
•
Delay from deassertion of internal PORESET to SPLL lock
•
•
CLKIN = 18 MHz
CLKIN = 75 MHz
CLKIN = 18 MHz
CLKIN = 75 MHz
SPLLMFCLK = 18 MHz
SPLLMFCLK = 25 MHz
PORESET
Reset Configuration
Input line sampled by the MSC8103 at the rising edge of
PORESET.
EONCE Event Bit 0
Input line sampled after SC140 core PLL locks. Holding EE0
high when PORESET is deasserted puts the SC140 into
Debug mode.
Host Port Enable
Input line sampled at the rising edge of PORESET. If
asserted, the Host port is enabled, the system data bus is
32-bit wide, and the Host must program the reset
configuration word.
Boot Mode
Input lines sampled at the rising edge of PORESET, which
determine the MSC8103 Boot mode.
external pin initiates the power-on reset flow.
Characteristics
MSC8103 Network Digital Signal Processor, Rev. 11
Description
Table 2-13.
RSTCONF
MODCK[1–3]
Table 2-14.
External Configuration Signals
pin. These pins are sampled at the rising edge of
) pins are sampled by the MSC8103. The signals on these
Reset Timing
0
1
0
1
0
1
00
01
10
11
Reset Configuration Master.
Reset Configuration Slave.
SC140 starts the normal processing
mode after reset.
SC140 enters Debug mode immediately
after reset.
Host port disabled (hardware reset
configuration enabled).
Host port enabled.
MSC8103 boots from external memory.
MSC8103 boots from HDI16.
Reserved.
Reserved.
800 / SPLLMFCLK
PORESET
1024 / CLKIN
Expression
16 / CLKIN
should be asserted externally for at
CC
Settings
. As Table 2-13 shows, the
888.8
213.3
Min
Freescale Semiconductor
56.89
13.65
44.4
32.0
Max
—
—
PORESET
EE[0–1]
Unit
,
ns
ns
µs
µs
µs
µs
. In