MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 44

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Physical and Electrical Specifications
2.5 Clock Configuration
The following sections provide a general description of clock configuration.
2.5.1
Table 2-6 shows the maximum frequency values for each rated core frequency (275 or 300 MHz). The user must
ensure that maximum frequency values are not exceeded.
Six bit values map the MSC8103 clocks to one of the valid configuration mode options. Each option determines the
CLKIN
dedicated input pins (
configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140, SCC
clocks, CPM parallel I/O ports, and system buses, the
MODCK_H values when the internal power-on reset (internal
changes only when the internal
• SPLL pre-division factor (SPLL PDF)
• SPLL multiplication factor (SPLL MF)
• Bus post-division factor (Bus DF)
• CPM division factor (CPM DF)
• Core division factor (Core DF)
• CPLL pre-division factor (CPLL PDF)
• CPLL multiplication factor (CPLL MF)
The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured through the
System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256.
Note: Refer to Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M (AN2306) for details on
2.5.2
This section describes the clock registers in detail. The registers discussed are as follows:
• System Clock Control Register (SCCR)
• System Clock Mode Register (SCMR)
2-4
Core Frequency
CPM Frequency (CPMCLK)
Bus Frequency (BCLK)
Serial Communication Controller Clock Frequency (SCLK)
Baud Rate Generator Clock Frequency (BRGCLK)
External Clock Output Frequency (CLKOUT)
, SC140, system bus, SCC clock, CPM, and
clock configuration.
Valid Clock Modes
Clocks Programming Model
MODCK[1–3]
Characteristic
PORESET
MSC8103 Network Digital Signal Processor, Rev. 11
) and three bits from the hard reset configuration word (MODCK_H). To
Table 2-6.
signal is deasserted. The following factors are configured:
CLKOUT
Maximum Frequencies
MODCK[1–3]
frequencies. The six bit values are derived from three
PORESET
pins are sampled and combined with the
) is deasserted. Clock configuration
183.33
91.67
91.67
91.67
91.67
Maximum Frequency in MHz
275
Freescale Semiconductor
300
200
100
100
100
100