RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 34

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
Table 10 Performance Counter Control
The performance counter interrupt will only occur when interrupts are enabled in the Status
register, IE=1, and Interrupt Mask bit 13 (IM[13]) of the coprocessor 0 interrupt control register is
not set.
PerfControl
Field
4..0
7..5
8
9
10
31..11
Description
Event Type
Reserved (must be zero)
Count in Kernel Mode
Count in User Mode
Count Enable
Reserved (must be zero)
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
0A:
0B:
0C: Data cache misses
0D: Data TLB misses
0E:
0F:
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
1B:
1C: Cache instruction stall cycles
1D: Multiplier stall cycles
1E:
0:
1:
0:
1:
0:
1:
Clock cycles
Total instructions issued
Floating-point instructions issued
Integer instructions issued
Load instructions issued
Store instructions issued
Dual issued pairs
Branch prefetches
External Cache Misses
Stall cycles
Secondary cache misses
Instruction cache misses
Instruction TLB misses
Joint TLB instruction misses
Joint TLB data misses
Branches taken
Branches issued
Secondary cache writebacks
Primary cache writebacks
Dcache miss stall cycles (cycles where both cache miss tokens taken and a third
address is requested)
Cache misses
FP possible exception cycles
Slip Cycles due to multiplier busy
Coprocessor 0 slip cycles
Slip cycles doe to pending non-blocking loads
Write buffer full stall cycles
Stall cycles due to pending non-blocking loads - stall start of exception
Disable
Enable
Disable
Enable
Disable
Enable
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
34