RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 31

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.30 Data Prefetch
Figure 10 Processor Block Write
Figure 11 Multiple Outstanding Reads
The RM7000 is the first PMC-Sierra design to support the MIPS IV integer data prefetch ( PREF )
and floating-point data prefetch ( PREFX ) instructions. These instructions are used by the
compiler or by an assembly language programmer when it is known or suspected that an upcoming
data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the
memory latency can be hidden under the execution of other instructions. If the execution of a
prefetch instruction would cause a memory management or address error exception the prefetch is
treated as a NOP .
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Master
SysClock
SysAD
SysCmd
RspSwap*
ValidOut*
ValidIn*
Release*
PRqst*
PAck*
TcMatch
Processor
Addr
Read
1
Write
1
Addr
Tertiary(Miss)
NData
Data0
Data0
1
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
NData
Data1
Data1
System
3
4
2
NData
Processor
Data2
Addr
Read
NEOD
Data3
2
2
5
Tertiary(Miss)
Data0
6
Data1
7
Data0
System
NData
Released
8
2
Data1
NData
31
2