RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 14

RM7000-300S

Manufacturer Part Number

RM7000-300S

Description

Manufacturer

PMC [PMC-Sierra, Inc]

Datasheet

1.RM7000-300S.pdf (54 pages)

Current page: 14 of 54
Download datasheet (836Kb)

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002175, Issue 1

4.4

Figure 4 Pipeline

Note that instruction dependencies, resource conflicts, and branches result in some of the

instruction slots being occupied by

Integer Unit

Like the RM5200 Fcamily, the RM7000 implements the MIPS IV Instruction Set Architecture,

and is therefore fully upward compatible with applications that run on processors such as the

R4650 and R4700 that implement the earlier generation MIPS III Instruction Set Architecture.

Additionally, the RM7000 includes two implementation specific instructions not found in the

baseline MIPS IV ISA, but that are useful in the embedded market place. Described in detail in a

later section, these instructions are integer multiply-accumulate and three-operand integer

multiply.

The RM7000 integer unit includes thirty-two general purpose 64-bit registers, the HI/LO result

registers for the two-operand integer multiply/divide operations, and the program counter, or PC.

There are two separate execution units, one of which can execute function, or F, type instructions

and one which can execute memory, or M, type instructions. See above for a description of the

instruction types and the issue rules. As a special case, integer multiply/divide instructions as well

as their corresponding MFHI and MFLO instructions can only be executed in the F type

execution unit. Within each execution unit the operational characteristics are the same as on

previous MIPS designs with single cycle ALU operations (add, sub, logical, shift), one cycle load

delay, and an autonomous multiply/divide unit.

The RM7000 has thirty-two general purpose registers with register location 0 (r0) hard wired to a

zero value. These registers are used for scalar integer operations and address calculation. In order

to service the two integer execution units, the register file has four read ports and two write ports

and is fully bypassed both within and between the two execution units to minimize operation

latency in the pipeline.

2A-2D:

1A-2A:

1I-1R:

2W:

2R:

1D:

1A:

2A:

2I:

Instruction cache access

Instruction virtual to physical address translation

Issue or slip decision, Branch decision

Data virtual address calculation

Integer add, logical, shift

Store Align

Data cache access and load align

Data virtual to physical address translation

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

NOP

one cycle

Released

RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 14

RM7000-300S

Related parts for RM7000-300S