RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 33

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.34 Performance Counters
Table 9 Watch Control Register
Like the Test/Break-point capability described above, the Performance Counter feature has been
added to improve the observability and controllability of the processor thereby easing system
debug and, especially in the case of the performance counters, easing system tuning.
The Performance Counter feature is implemented using two new CP0 registers, PerfCount and
PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit
31 is set. The PerfControl register is a 32-bit register containing a five bit field which selects one
of twenty-two event types as well as a handful of bits which control the overall counting function.
Note that only one event type can be counted at a time and that counting can occur for user code,
kernel code, or both. The event types and control bits are listed in Table 10.
Register
Watch1, 2
Watch Mask Mask
63
Store
31:2
Bit Field/Function
62
Load
61
Instr
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
60:36
0
35:2
Addr
1
Mask
Watch
2
1:0
0
0
Mask
Watch
1
Released
33