m28f008 Intel Corporation, m28f008 Datasheet - Page 9

• Manufacturer Part Number: m28f008
• Description: 8 Mbit 1 Mbit X 8 Flash Memory
• Manufacturer: Intel Corporation

the Read Array command until the WSM has com-
pleted its operation The Read Array command is
functional when V
Intelligent Identifier Command
The M28F008 contains an intelligent identifier oper-
ation initiated by writing 90H into the Command
User Interface Following the command write a read
cycle from address 00000H retrieves the manufac-
turer code of 89H A read cycle from address 01H
returns the device code of A2H To terminate the
operation it is necessary to write another valid com-
mand into the register Like the Read Array com-
mand the intelligent identifier command is functional
when V
Read Status Register Command
The M28F008 contains a Status Register which may
be read to determine when a byte write or block
erase operation is complete and whether that oper-
ation completed successfully The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In-
terface After writing this command all subsequent
read operations output data from the Status Regis-
ter until another valid command is written to the
SR 2–SR 0
SR 7
SR 6
SR 5
SR 4
SR 3
1
0
1
0
1
0
1
0
1
0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
PP
These bits are reserved for future use and
should be masked out when polling the Status
Register
WRITE STATE MACHINE STATUS
Ready
Busy
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress Completed
ERASE STATUS
Error in Block Erasure
Successful Block Erase
BYTE WRITE STATUS
Error in Byte Write
Successful Byte Write
V
V
V
e
PP
PP
PP
e
V
STATUS
Low Detect Operation Abort
OK
RESERVED FOR FUTURE
ENHANCEMENTS
PPL
PP
or V
e
WSMS
PPH
7
V
PPL
or V
ESS
6
PPH
Table 4 Status Register Definitions
ES
5
BWS
4
VPPS
NOTES
RY BY or the Write State Machine Status bit must first
be checked to determine byte write or block erase com-
pletion before the Byte Write or Erase Status bit are
checked for success
If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt an improper command se-
quence was entered Attempt the operation again
If V
cleared before another byte write or block erase opera-
tion is attempted
The V
provide continuous indication of V
terrogates the V
erase command sequences have been entered and in-
forms the system if V
V
back between V
Command User Interface The contents of the
Status Register are latched on the falling edge of OE
or CE whichever occurs last in the read cycle OE or
CE must be toggled to V
update the Status Register latch The Read Status
Register command functions when V
V
Clear Status Register Command
The Erase Status and Byte Write Status bits are set
to ‘‘1’’s by the Write State Machine and can only be
reset by the Clear Status Register Command These
bits indicate various failure conditions (see Table 4)
By allowing system software to control the resetting
of these bits several operations may be performed
(such as cumulatively writing several bytes or eras-
ing multiple blocks in sequence) The Status Regis-
ter may then be polled to determine if an error oc-
curred during that sequence This adds flexibility to
the way the device may be used
Additionally the V
set by system software before further byte writes or
block erases are attempted To clear the Status
Register the Clear Status Register command (50H)
is written to the Command User Interface The Clear
Status Register command is functional when V
V
3
PP
PPH
PPL
PP
Status bit is not guaranteed to report accurate feed-
low status is detected the Status Register must be
PP
or V
Status bit unlike an A D converter does not
R
2
PPH
PP
PPL
level only after the byte write or block
and V
R
1
PP
PP
Status bit (SR 3) MUST be re-
has not been switched on The
PPH
IH
R
0
before further reads to
PP
level The WSM in-
PP
e
M28F008
V
PPL
PP
e
or
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