m28f008 Intel Corporation, m28f008 Datasheet - Page 8

• Manufacturer Part Number: m28f008
• Description: 8 Mbit 1 Mbit X 8 Flash Memory
• Manufacturer: Intel Corporation

M28F008
NOTES
1 Bus operations are defined in Table 2
2 IA
3 SRD
4 Following the intelligent identifier command two read operations access manufacture and device codes
5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command
6 Commands other than those shown above are reserved by Intel for future device implementations and should not be
used
Write
Writes to the Command User Interface enable read-
ing of device data and intelligent identifier They also
control inspection and clearing of the Status Regis-
ter Additionally when V
User Interface controls block erasure and byte write
The contents of the interface register serve as input
to the internal write state machine
The Command User Interface itself does not occupy
an addressable memory location The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written
The Command User Interface is written by bringing
WE to a logic-low level (V
dresses and data are latched on the rising edge of
WE Standard microprocessor write timings are
used
8
Read Array Reset
Intelligent Identifier
Read Status Register
Clear Status Register
Erase Setup Erase Confirm
Erase Suspend Erase Resume
Byte Write Setup Write
Alternate Byte Write Setup Write
BA
WA
WD
IID
e
e
e
e
e
e
Identifier Address 00H for manufacturer code 01H for device code
Data read from intelligent identifiers
Address within the block being erased
Address of memory location to be written
Data to be written at location WA Data is latched on the rising edge of WE
Data read from Status Register See Table 4 for a description of the Status Register bits
Command
PP
IL
e
) while CE is low Ad-
V
PPH
Cycles
Req’d
Bus
1
3
2
1
2
2
2
2
the Command
Table 3 Command Definitions
Notes
2 3 4
2 3 5
2 3 5
1
3
2
Operation Address Data Operation Address Data
Write
Write
Write
Write
Write
Write
Write
Write
Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations Figure 9 for specific tim-
ing parameters
COMMAND DEFINITIONS
When V
tions from the Status Register intelligent identifier
or array blocks are enabled Placing V
enables successful byte write and block erase oper-
ations as well
Device operations are selected by writing specific
commands into the Command User Interface Table
3 defines the M28F008 commands
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode the M28F008 defaults to Read
Array mode This operation is also initiated by writing
FFH into the Command User Interface Microproces-
sor read cycles retrieve array data The device re-
mains enabled for reads until the Command User
Interface contents are altered Once the internal
Write State Machine has started a block erase or
byte write operation the device will not recognize
First Bus Cycle
PPL
WA
WA
BA
X
X
X
X
X
is applied to the V
FFH
B0H
90H
70H
50H
20H
40H
10H
Read
Read
Write
Write
Write
Write
Second Bus Cycle
PP
pin read opera-
WA
WA
BA
IA
X
X
PPH
on V
SRD
D0H
D0H
WD
WD
IID
PP