s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 83

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
ADD-ON INTERRUPT CONTROL/STATUS
REGISTER (AINT)
Figure 35. Add-On Interrupt Control/Status Register
AMCC Confidential and Proprietary
Register Name
Add-On
Address Offset
Power-up value
Attribute
Size
Outgoing Mailbox
Interrupt (R/WC)
Incoming Mailbox
Interrupt (R/WC)
BIST (R/WC)
Read Transfer
Complete (R/WC)
Write Transfer
Complete (R/WC)
Interrupt Asserted (RO)
Bus Mastering
Error Interrupt (R/WC)
31
0 0 0 0 0 0 0 0
Add-On Interrupt Control and Status
38h
00000000h
Read/Write, Read/Write_One_Clear
32 bits
Interrupt Status
24 23
0
21
201918
17
16 1514
0
12
Interrupt on Write
Transfer Complete
Interrupt on Read
Transfer Complete
Interrupt Selection
This register provides the method for choosing which
conditions are to produce an interrupt on the Add-On
bus interface, a method for viewing the cause for the
interrupt, and a method for acknowledging (removing)
the interrupt’s assertion.
Interrupt sources:
8
•
•
•
•
•
•
0 0 0
One of the Incoming mailboxes (1,2,3 or 4)
becomes full.
One of the Outgoing mailboxes (1,2,3 or 4)
becomes empty.
Built-in self test issued.
Write Transfer Count = zero
Read Transfer Count = zero
Target/Master Abort
4
Interrupt Source (R/W)
Enable & Selection
D4-D0 Incoming Mailbox
D4=Enable Interrrupt
D3-D2=Mailbox #
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
D0-D1=Byte #
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
D12-D8 Outgoing Mailbox (R/W)
D12=Enable Interrupt
D11-D10=Mailbox
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
D9-D8=Byte #
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
0 Bit
Revision 1.02 – June 27, 2006
(Becomes Full)
(Goes empty)
Value
Data Book
DS1527
83