s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 25

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
System Pins — PCI Local Bus
Interface Control Pins — PCI Bus Signal
Arbitration Pins (Bus Masters Only) — PCI Local Bus
Error Reporting Pins — PCI Local Bus
AMCC Confidential and Proprietary
Signal
DEVSEL#
Signal
PERR#
REQ#
GNT#
Signal
RST#
FRAME#
CLK
TRDY#
STOP#
LOCK#
Signal
IRDY#
IDSEL
Type
Type
Type
out
s/t/s
in
in
in
Type
s/t/s
s/t/s
s/t/s
s/t/s
s/t/s
in
in
Clock. The rising edge of this signal is the reference upon which all other signals are based, with the
exception of RST# and the interrupt (IRQA#-). The maximum frequency for this signal is 33 MHz and the
minimum is DC (0 Hz).
Reset. This signal is used to bring all other signals within this device to a known, consistent state. All PCI
bus interface output signals are not driven (tri-stated), and open drain signals such as SERR# are floated.
Request. This signal is sourced by an agent wishing to become the bus master. It is a point-to-point signal
and each master has its own REQ#.
Grant. The GNT# signal is a dedicated, point-to-point signal provided to each potential bus master and sig-
nifies that access to the bus has been granted.
Parity Error. This pin is used for reporting parity errors during the data portion of a bus transaction for all
cycles except a Special Cycle. It is sourced by the agent receiving data and driven active two clocks fol-
lowing the detection of the error. This signal is driven inactive (high) for one clock cycle prior to returning to
the tri-state condition.
Frame. This signal is driven by the current bus master and identifies both the beginning and duration of
a bus operation. When FRAME# is first asserted, it indicates that a bus transaction is beginning and
that valid addresses and a corresponding bus command are present on the AD[31:00] and C/BE[3:0]
lines. FRAME# remains asserted during the data transfer portion of a bus operation and is deasserted
to signify the final data phase.
Initiator Ready. This signal is sourced by the bus master and indicates that the bus master is able to
complete the current data phase of a bus transaction. For write operations, it indicates that valid data is
on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted together.
Target Ready. This signal is sourced by the selected target and indicates that the target is able to com-
plete the current data phase of a bus transaction. For read operations, it indicates that the target is pro-
viding valid data on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted
together.
Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop
the current transaction.
Lock. The lock signal provides for the exclusive use of a resource. The S5935 may be locked as a tar-
get by one master at a time. The S5935 cannot lock a target when it is a master.
Initialization Device Select. This pin is used as a chip select during configuration read or write opera-
tions.
Device Select. This signal is sourced by an active target upon decoding that its address and bus com-
mands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle.
Description
Description
Description
Description
Revision 1.02 – June 27, 2006
Data Book
DS1527
25