s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 46
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s5935qrc
Manufacturer Part Number
s5935qrc
Description
Pci Product
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.S5935QRC.pdf
(204 pages)
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S5935 – PCI Product
LATENCY TIMER REGISTER (LAT)
Figure 15. Latency Timer Register
46
Register Name
Address Offset
Power-up value
Boot-load
Attribute
Size
DS1527
7
X
Latency Timer
0Dh
00h
External nvRAM offset 04Dh
Read/Write, bits 7:3; Read Only bits
2:0
8 bits
X
6
X
5
4
X
3
X
The latency timer register has meaning only when this
controller is used as a bus master and pertains to the
number of PCI bus clocks that this master will be guar-
anteed. The nonzero value for this register is internally
decremented after this device has been granted the
bus and has begun to assert FRAME#. Prior to this
latency timer count reaching zero, this device can
ignore the removal of the bus grant and may continue
the use of the bus for data transfers.
2
0
Latency Timer value (R/W)
# of clocks x 8
1
0
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
0
0
Data Book
Bit
Value
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