s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 143

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
the FIFO condition after it advances, and are updated
off of the rising edge of BPCLK. When RDFIFO# is
deasserted, the DQ bus floats. The next time
RDFIFO# is asserted, data 2 is presented on the DQ
bus (as there was no BPCLK edge to advance the
FIFO).
A synchronous FIFO interface has the advantage of
allowing data to be accessed more quickly (in bursts)
by the Add-On. As a target, if a full S5935 FIFO is writ-
Figure 78. Synchronous FIFO Register Burst Read Access Example
AMCC Confidential and Proprietary
RDEMPTY
SELECT#
ADR[6:2]
DQ[31:0]
BE[3:0]#
BPCLK
RD#
Status Before Read
Data 0
Valid Byte Enables
Valid Address
Data 1
ten (or an empty FIFO is read) by a PCI initiator, the
S5935 requests a retry. The faster the Add-On inter-
face can empty (or fill) the FIFO, the less often retries
occur. With the S5935 as a PCI initiator, a similar situ-
ation occurs. Not emptying or filling the FIFO quickly
enough results in the S5935 giving up control of the
PCI bus. Higher PCI bus data transfer rates are possi-
ble through the FIFO with a synchronous interface.
New Status
FIFO Pointer Advances
Data 2
New Status
Revision 1.02 – June 27, 2006
Data Book
DS1527
143