s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 60

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
The PCI bus operation registers are mapped as 16
consecutive DWORD registers located at the address
space (I/O or memory) specified by the Base Address
Register 0. These locations are the primary method of
communication between the PCI and Add-On buses.
Data, software-defined commands and command
Table 30. Operation Registers — PCI Bus
60
DS1527
Address Offset
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
Abbreviation
INTCSR
MWAR
MWTC
MRAR
MRTC
MCSR
OMB1
OMB2
OMB3
OMB4
MBEF
IMB1
IMB2
IMB3
IMB4
FIFO
Outgoing Mailbox Register 1
Outgoing Mailbox Register 2
Outgoing Mailbox Register 3
Outgoing Mailbox Register 4
Incoming Mailbox Register 1
Incoming Mailbox Register 2
Incoming Mailbox Register 3
Incoming Mailbox Register 4
FIFO Register port (bidirectional)
Master Write Address Register
Master Write Transfer Count Register
Master Read Address Register
Master Read Transfer Count Register
Mailbox Empty/Full Status
Interrupt Control/Status Register
Bus Master Control/Status Register
parameters can be either exchanged through the mail-
boxes, transferred through the FIFO in blocks under
program control, or transferred using the FIFOs under
Bus Master control. Table 1 lists the PCI Bus Opera-
tion Registers.
Register Name
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book