MK30DN512ZVLQ10 Freescale Semiconductor, MK30DN512ZVLQ10 Datasheet - Page 57

• Manufacturer Part Number: MK30DN512ZVLQ10
• Description: Specifications: Program Memory Size: 512KB (512K x 8) ; RAM Size: 128K x 8 ; Number of I /O: 102 ; Package / Case: 144-LQFP ; Speed: 100MHz ; Oscillator Type: Internal ; Packaging: Tray ; Program Memory Type: FLASH ; EEPROM Size: - ; Core Processor:
• Manufacturer: Freescale Semiconductor

RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Freescale Semiconductor, Inc.
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Num
Num
S10
S11
S1
S2
S3
S4
S5
S6
S7
S8
S9
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
Operating voltage
I2S_BCLK cycle time (input)
Description
Description
S5
S7
K30 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
S4
Figure 24. I
Table 43. I
S9
Table 44. I
S9
S1
Table continues on the next page...
S3
S2
S10
2
S timing — master mode
2
S master mode timing
2
S slave mode timing
S4
S2
S8
S7
Peripheral operating requirements and behaviors
2 x t
5 x t
8 x t
45%
45%
Min.
Min.
-2.5
2.7
2.7
20
—
—
-3
0
SYS
SYS
SYS
Max.
55%
55%
Max.
3.6
3.6
15
15
—
—
—
—
—
—
MCLK period
S10
BCLK period
S6
S8
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
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