adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 9

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

SHARC MEL-100 MEMORY AND I/O INTERFACE
FEATURES
The SHARC Mel-100 adds the following architectural features
to the ADSP-2116x family core:
On-Chip Memory
The SHARC Mel-100 contains 0.5 Mbit of on-chip SRAM.
Off-Chip Memory and Peripherals Interface
The SHARC Mel-100’s external port provides the processor’s
interface to off-chip memory and peripherals. The 62.7 Mword
off-chip address space (254 Mword if all SDRAM) is included in
the SHARC Mel-100 processor’s unified address space. The
separate on-chip buses—for PM addresses, PM data, DM
addresses, DM data, I/O addresses, and I/O data—are
multiplexed at the external port to create an external system bus
with a single 24-bit address bus and a single 32-bit data bus.
Every access to external memory is based on an address that
fetches a 32-bit word. When fetching an instruction from
external memory, two 32-bit data locations are being accessed
for packed instructions. Unused link port lines can also be used
as additional data lines DATA[0]–DATA[15], enabling single-
cycle execution of instructions from external memory at up to
100 MHz. Figure 6 shows the alignment of various accesses to
external memory.
The external port supports asynchronous, synchronous, and
synchronous burst access. Synchronous burst SRAM can be
interfaced gluelessly. The SHARC Mel-100 can also interface
gluelessly to SDRAM. Addressing of an external memory device
is facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. The SHARC Mel-100
provides programmable memory wait states and external
memory acknowledge controls to enable interfacing to memory
and peripherals with variable access, hold, and disable time
requirements.
47
FLOAT OR FIXED, D31–D0, 32-BIT PACKED
32-BIT PACKED INSTRUCTION
40 39
16-BIT PACKED INSTRUCTION EXECUTION
Figure 6. External Data Alignment Options
8-BIT PACKED INSTRUCTION EXECUTION
48-BIT INSTRUCTION FETCH
(NO PACKING)
16-BIT PACKED DMA DATA
DATA 47
32 31
8-BIT PACKED DMA DATA
–
16
24 23
PROM BOOT
16 15
EXTRA DATA LINES DATA[15
ARE ONLY ACCESSIBLE IF
LINK PORTS ARE DISABLED.
ENABLE THESE ADDITIONAL
DATA LINES BY SELECTING
IPACK[1:0] = 01 IN SYSCON
L1DATA[7:0]
DATA 15 – 8
DATA 15
8 7
L0DATA[7:0]
DATA7 – 0
–
0
–
0]
0
Rev. 0 | Page 9 of 28
SDRAM Interface
The SDRAM interface enables the SHARC Mel-100 to transfer
data to and from synchronous DRAM (SDRAM) at the core
clock frequency or one-half the core clock frequency. The
synchronous approach, coupled with the core clock frequency,
supports data transfer at a high throughput—up to
400 Mbytes/s for 32-bit transfers and 600 Mbytes/s for 48-bit
transfers. The SDRAM interface provides a glueless interface
with standard SDRAMs (16 Mbit, 64 Mbit, 128 Mbit, and
256 Mbit) and includes options to support additional buffers
between the SHARC Mel-100 and SDRAM. The SDRAM
interface is extremely flexible and provides capability for
connecting SDRAMs to any one of the SHARC Mel-100
processor’s four external memory banks, with up to all four
banks mapped to SDRAM. Systems with several SDRAM
devices connected in parallel may require buffering to meet
overall system timing requirements. The SHARC Mel-100
supports pipelining of the address and control signals to enable
such buffering between itself and multiple SDRAM devices.
Target Board JTAG Emulator Connector
Analog Devices’ DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the SHARC Mel-100
processor to monitor and control the target board processor
during emulation. Analog Devices’ DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
enabling inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that
the emulator will not affect target system loading or timing. For
complete information on Analog Devices’ DSP Tools product
line of JTAG emulator operation, see the appropriate Emulator
Hardware User's Guide. For detailed information on the
interfacing of Analog Devices’ JTAG emulators with Analog
Devices’ DSP products with JTAG emulation ports, please refer
to the Engineer-to-Engineer Note EE-68, Analog Devices JTAG
Emulation Technical Reference. Both of these documents can be
found on the Analog Devices website at:
http://www.analog.com/dsp/tech_docs.html
DMA Controller
The SHARC Mel-100 processor’s on-chip DMA controller
enables zero-overhead data transfers without processor
intervention. The DMA controller operates independently and
invisibly to the processor core, enabling DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the SHARC
Mel-100 processor’s internal memory and external memory,
external peripherals, or a host processor. DMA transfers can
also occur between the SHARC Mel-100 processor’s internal
memory and its serial ports, link ports, or the SPI (serial
peripheral interface) compatible port. External bus packing and
unpacking of 16-, 32-, 48-, or 64-bit words in internal memory
is performed during DMA transfers from either 8-, 16-, or 32-
bit wide external memory. Fourteen channels of DMA are
ADSST-SHARC-Mel-100