adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet
adsst-sharc-melody-ultra
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adsst-sharc-melody-ultra Summary of contents
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... SHIFTER ALU Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 ® SHARC Melody Audio Processor ADSST-SHARC-Melody-Ultra 2 S support via 8 programmable and TEST & EMULATION I/O PORT DATA ADDR DATA DATA ADDR CONTROLLER IOD ...
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... ADSST-SHARC-Melody-Ultra TABLE OF CONTENTS Key Features ...................................................................................... 3 General Description ......................................................................... 4 Hardware Architecture ................................................................ 4 Software Architecture .................................................................. 5 SHARC Melody Ultra Family Core Architecture..................... 6 SHARC Melody Ultra Memory and I/O Interface Features ... 9 Pin Function Descriptions ............................................................ 13 Boot Modes ................................................................................. 18 Specifications................................................................................... 19 Recommended Operating Conditions .................................... 19 Electrical Characteristics ........................................................... 20 REVISION HISTORY Revision 0: Initial Version Absolute Maximum Ratings ......................................................... 21 Timing Specifications ...
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... HDCD Delay Management Bass Management MPEG-2 AAC WaveSurround® virtual loudspeaker, virtual headphone Downsampling 96 kHz to 48 kHz (2-channel) ADSST-SHARC-Melody-Ultra Encoders: Dolby Digital Consumer Encoder Single-chip DSP based implementation of digital audio algorithms SHARC Melody Ultra processor features 100 MIPS and extensive on-chip memory ...
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... ADSST-SHARC-Melody-Ultra GENERAL DESCRIPTION The SHARC Melody Ultra family of powerful 32-bit audio processors from Analog Devices enables flexible designs and delivers a host of features across high-end and high fidelity audio systems to the AV receiver and DVD markets. It includes multichannel audio decoders, encoders, and postprocessors for digital audio designs using DSPs in home theater systems and automotive audio receivers ...
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... The SHARC Melody Ultra software has the following parts: • Executive kernel • Algorithm as library module ADSST-SHARC-Melody-Ultra Figure 1 ) The executive kernel has the following functions: • Power-up hardware initialization • ...
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... ADSST-SHARC-Melody-Ultra The SHARC Melody Ultra continues the SHARC’s industry- leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include a 1 Mbit dual-ported SRAM memory, a host processor interface, an I/O processor that sup- ports 14 DMA channels, four serial ports, two link ports, an SDRAM controller, an SPI interface, an external parallel bus, and glueless multiprocessing ...
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... Fourier transforms. The two DAGs of the SHARC Melody Ultra contain sufficient registers to enable the creation circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer Rev Page ADSST-SHARC-Melody-Ultra CS BOOT ADDR EPROM (OPTIONAL) ...
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... ADSST-SHARC-MELODY-ULTRA WITH ID = 011 IOP REGISTERS OF MULTIPROCESSOR ADSST-SHARC-MELODY-ULTRA MEMORY WITH ID = 100 SPACE IOP REGISTERS OF ADSST-SHARC-MELODY-ULTRA WITH ID = 101 IOP REGISTERS OF ADSST-SHARC-MELODY-ULTRA WITH ID = 110 RESERVED Melody Ultra can conditionally execute a multiply, an add, and a subtract in both processing elements, while branching, all within a single instruction. ADDRESS 0x0000 0000 – ...
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... Unused link port lines can also be used as additional data lines DATA[0]–DATA[15], enabling single-cycle execution of instructions from external memory 100 MHz. Figure 6 shows the alignment of various ac- cesses to external memory. ADSST-SHARC-Melody-Ultra DATA 47 – ...
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... ADSST-SHARC-Melody-Ultra Target Board JTAG Emulator Connector Analog Devices’ DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the SHARC Melody Ultra processor to monitor and control the target board proces- sor during emulation. Analog Devices’ DSP Tools product line ...
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... Select ( BMS ), EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins. 8-, 16-, or 32-bit host processors can also be used for booting. ADSST-SHARC-Melody-Ultra Phased-Locked Loop and Crystal Double Enable The SHARC Melody Ultra uses an on-chip phase-locked loop (PLL) to generate the internal clock for the core. The CLK_CFG[1:0] pins are used to select ratios of 2:1, 3:1, and 4:1 ...
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... ADSST-SHARC-Melody-Ultra Power Supplies The SHARC Melody Ultra has separate power supply connec- tions for the internal (V ), external (V DDINT (AV /AGND) power supplies. The internal and analog supplies DD must meet the 1.8 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same supply ...
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... Figure 9. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place) Table or GND, except DDEXT Figure 10. JTAG Target Board Connector with No Local Boundary Scan EMU GND TMS TCK TRST TDI TDO Rev Page ADSST-SHARC-Melody-Ultra 1 2 GND EMU 3 4 GND KEY (NO PIN BTMS TMS 7 ...
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... ADSST-SHARC-Melody-Ultra The following symbols appear in the Type column of A Asynchronous, G Ground, I Input, O Output, P Power Supply, S Synchronous, (A/D) Active Drive, (O/D) Open Drain, T Three-State (when SBTS is asserted or when the SHARC Melody Ultra is a bus slave). Table 2. Pin Function Description Mnemonic Type Function ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access ...
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... For example, this enables the use MHz crystal to enable DDEXT CLK_CFG1 CLK_CFG0 Core:CLKIN 8:1 Rev Page ADSST-SHARC-Melody-Ultra CLKIN:CLKOUT 1× 1× 1× 2× 2× 2× ...
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... ADSST-SHARC-Melody-Ultra Mnemonic Type Function DMAG1 O/T DMA Grant 1 (DMA Channel 11). Asserted by SHARC Melody Ultra to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0 = 00x. ...
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... If the SHARC Melody Ultra attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor/SHARC Melody Ultra deadlock. ADSST-SHARC-Melody-Ultra Rev Page ...
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... ADSST-SHARC-Melody-Ultra Mnemonic Type Function SCLKx I/O Transmit/Receive Serial Clock (Serial Ports 3). Each SCLK pin has an internal pull-up resistor. This signal can be either internally or externally generated. SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host accesses. SDCLK0 I/O/S/T SDRAM Clock Output 0 ...
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... BRST, FSx, DxA, DxB, SCLKx, RAS , CAS , SDWE , SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS , EBOOT, LBOOT, BMS , SDCKE, CLK_CFGx, CLKDBL , CLKIN, RESET , TRST, TCK, TMS, TDI. 2 See the Th ermal Characteristics section on page 24 for information on thermal specifications. Test Conditions Min max 2.0 DDEXT min DDEXT 2 –40 Rev Page ADSST-SHARC-Melody-Ultra C Grade K Grade Max Min Max 1.71 1.89 1.71 1.89 1.71 1.89 1.71 1.89 3.13 3.47 3.13 3. 0.5 2 ...
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... ADSST-SHARC-Melody-Ultra ELECTRICAL CHARACTERISTICS Table 5. Parameter V High Level Output Voltage OH V Low Level Output Voltage High Level Input Current Low Level Input Current IL I CLKIN High Level Input Current IHC I CLKIN Low Level Input Current ILC I Keeper High Load Current ...
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... LxCLKD for the link ports). CLKIN (4.2MHz–50MHz) XTAL QUARTZ CRYSTAL OR CRYSTAL OSCILLATOR Rev Page ADSST-SHARC-Melody-Ultra Table determine switching frequencies for EP: MULTIPROCESSING HOST SRAM SBSRAM PLLICLK (8.4MHz–50MHz) LINK PORT: × ...
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... ADSST-SHARC-Melody-Ultra POWER DISSIPATION Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation depends on the instruction execution sequence and the data operands involved. Using the current specifications (I DD-INPEAK I ) from the ...
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... V OH (MEASURED) 2.0V 1. (MEASURED) OUTPUT STARTS DRIVING 50Ω 1.5V Figure 19. Typical Output Rise/Fall Time (20%–80%, V 1.5V Figure 20. Typical Output Rise/Fall Time (20%–80%, V Rev Page ADSST-SHARC-Melody-Ultra 0.0835X – 2.42 5 – 120 150 LOAD CAPACITANCE (pF) Figure 18. Typical Output Delay or Hold vs. Load Capacitance ...
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... ADSST-SHARC-Melody-Ultra ENVIRONMENTAL CONDITIONS Thermal Characteristics The SHARC Melody Ultra is packaged in a 225-lead Mini Ball Grid Array (MBGA). The SHARC Melody Ultra is specified for a case temperature ( ensure that the T CASE is not exceeded, a heat sink and/or an airflow source may be used. Use the center block of ground pins (MBGA balls: F6–10, G6– ...
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... J10 GND V J11 V DDINT DDEXT DATA[37] J12 DATA[26] DATA[40] J13 DATA[24] DATA[38] J14 DATA[25] DATA[36] J15 DATA[27] Rev Page ADSST-SHARC-Melody-Ultra PBGA Pin PBGA Pin Number Mnemonic Number K01 TIMEXP N01 K02 ADDR[22] N02 K03 ADDR[20] N03 K04 ADDR[23] N04 K05 V ...
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... ADSST-SHARC-Melody-Ultra PIN LAYOUT SUMMARY Figure 21. 225-Lead Metric MBGA Pin Assignments, Bottom View, Summary KEY GND DDINT V AGND DDEXT 1 USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO THE PRINTED CIRCUIT BOARD GROUND PLANE Rev Page ...
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... BSC 1.00 BSC TOP VIEW DETAIL A SEATING PLANE Figure 22. 225-Ball Mini-Ball Grid Array [MBGA] (CA-225) Dimensions shown in millimeters Instruction Rate 100 MHz 100 MHz Rev Page ADSST-SHARC-Melody-Ultra PIN 1 CORNER 15 1413 12 1110 ...
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... ADSST-SHARC-Melody-Ultra NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03373–0–10/03(0) Rev Page ...