adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 5

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

The SHARC Mel-100 processor can be interfaced to external
peripherals with relative ease. The communication between the
SHARC Mel-100 processor and a host microcontroller utilizes
the SPI bus. The host microcontroller can be the master and the
SHARC Mel-100 processor can act as a slave. The peripherals
can be controlled by the host microcontroller using the SPI bus.
The communication is based on commands and parameters.
Status information regarding the SHARC Mel-100 decoding is
periodically updated and made available to the host
microcontroller.
The block diagram of the SHARC Mel-100 (see Figure 1)
illustrates the following architectural features:
We will use Figure 2 as our reference. The SHARC Mel-100
communicates with the host microcontroller using SPI. The
SHARC Mel-100 has an on-chip memory buffer that is used for
storing commands/parameters sent by the host to the SHARC
Mel-100 and also status information from the SHARC Mel-100.
There is a defined protocol for passing commands and
obtaining status information. Once the SHARC Mel-100
receives a command from the host micro, it will process the
command and inform the host micro about the status. These
commands initiate actions such as encoding and decoding.
Encoding and decoding will result in data processing and the
processed data may be delivered over the serial port. For
example, while encoding, the MP3 data is accepted through the
serial port from peripherals like an ADC or S/PDIF receiver.
The MP3 data is then encoded and stored in an on-chip
compressed data buffer. The SHARC Mel-100 will prepare the
compressed frames in IEC 958 format so that they can be sent
out using the serial port or S/PDIF transmitter. Using the serial
port, compressed frames can be downloaded to the SHARC
Mel-100, where they can be decoded, and the resulting MP3
data can be sent on the serial port transmitter. While commands
and data are transferred between the host microcontroller and
the SHARC Mel-100 over the SPI, reliable communication
needs the help of interrupts and a few general-purpose
input/output lines.
• Computation units (ALU, multiplier, and shifter) with a
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• Timers with event capture modes
• On-chip, dual-ported SRAM
• External port for interfacing to off-chip memory and
• Host port and SDRAM interface
• DMA controller
• Enhanced serial ports
• JTAG test access port
shared data register file
peripherals
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SOFTWARE ARCHITECTURE
The audio processors from Analog Devices enable designers to
make value additions to product features working off the high-
end base functionality. The SHARC Mel-100 software has the
following parts:
The executive kernel has the following functions:
The executive kernel gets executed as soon as booting takes
place. The hardware resources are initialized in the beginning.
The command buffer and general-purpose programmable flag
pins are initialized. Various data buffers and memory variables
are initialized. Interrupts are programmed and enabled. Then,
definite signatures are written “Command buffer” to inform the
host that the SHARC Mel-100 is ready to receive the
commands. Once commands are issued by the host
microcontroller, they are executed and appropriate actions take
place. Decoding is handled by issuing appropriate commands
from the host microcontroller.
The kernel communicates with the library module for a
particular algorithm in a defined way. The details are found in
the specific implementation documents. As the kernel is
modular, it is easy to customize to different hardware platforms.
Most of the time, users need to change the initialization code to
suit the particular codec chosen.
The SHARC Mel-100 includes a 100 MHz core, dual-ported on-
chip SRAM, an integrated I/O processor with multiprocessing
support, and multiple internal buses to eliminate I/O
bottlenecks. The SHARC Mel-100 offers a Single-Instruction-
Multiple-Data (SIMD) architecture, using two computational
units. Fabricated in a state-of-the-art, high speed, low power
CMOS process, the SHARC Mel-100 has a 10 ns instruction
cycle time.
INPUT STREAM
• Executive kernel
• Algorithm as library module
• Power-up hardware initialization
• Serial port management
• Automatic stream detect
• Automatic code load
• Command processing
• Interrupt handling
• Data buffer management
• Calling library module
• Status report
EXECUTIVE KERNEL
Figure 3. Software
DECODING
ADSST-SHARC-Mel-100
LIBRARY
OUTPUT STREAM