adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 15

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

DMAR1
DMAR2
DQM
DxA
DxB
EBOOT
EMU
FLAG11–0
FSx
GND
HBG
HBR
ID2–0
IRQ2–0
LBOOT
LxACK
LxCLK
LxDAT7–0
[DATA15–0]
I/A
I/A
O/T
I/O
I/O
I
(O/D)
I/O/A
I/O
G
I/O
I/A
I
I/A
I
I/O
I/O
I/O
[I/O/T]
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has a
20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0 = 00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has a
20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0 = 00x.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command and
during SDRAM power-up initialization.
Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
EPROM Boot Select. For a description of how this pin operates, see Table 3 on page 17. This signal is a
system configuration selection that should be hardwired.
Emulation Status. Must be connected to the SHARC Mel-100 Analog Devices’ DSP Tools product line of JTAG
emulators target board connector only. EMU has an internal pull-up resistor.
Flag Pins. Each pin is configured via control bits as either an input or output. As an input, it can be tested as a
condition. As an output, it can be used to signal external peripherals.
Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally. It can be active high or low or an early or late frame
sync, in reference to the shifting of serial data.
Power Supply Return (26 pins).
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of
the external bus. HBG is asserted (held low) by the SHARC Mel-100 until HBR is released. In a multiprocessing
system, HBG is output by the SHARC Mel-100 bus master and is monitored by all others. After HBR is asserted,
and before HBG is given, HBG will float for 1 t
pulled up with a 20 kΩ to 50 kΩ external resistor.
Host Bus Request. Must be asserted by a host processor to request control of the SHARC Mel-100 processor’s
external bus. When HBR is asserted in a multiprocessing system, the SHARC Mel-100 that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the SHARC Mel-100 places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all SHARC Mel-100 bus requests (BR6–1) in a
multiprocessing system.
Multiprocessing ID. Determines which multiprocessing bus request (BR6–1) is used by the SHARC Mel-100.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or ID = 001 in single-
processor systems. These lines are a system configuration selection that should be hardwired or only
changed at reset.
Interrupt Request Lines. These pins are sampled on the rising edge of CLKIN and may be either edge-
triggered or level-sensitive.
Link Boot. For a description of how this pin operates, see Table 3 on page 17. This signal is a system
configuration selection that should be hardwired.
Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 kΩ resistor that is
enabled or disabled by the LxPDRDE bit of the LCTL register.
Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 kΩ resistor that is enabled or
disabled by the LxPDRDE bit of the LCTL register.
Link Port Data (Link Ports 0–1).
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data
pin, or a 20 kΩ internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
For silicon revisions 0.3, 1.0, and 1.1, each LxDAT pin has a 50 kΩ internal pull-down resistor that is enabled or
disabled by the LxPDRDE bit of the LCTL register.
Note that L1DATA[7:0] are multiplexed with the DATA[15:8] pins; L0DATA[7:0] are multiplexed with the
DATA[7:0] pins. If link ports are disabled and are not be used, these pins can be used as additional data lines
for executing instructions at up to the full clock rate from external memory. See DATA47–16 for more
information.
Rev. 0 | Page 15 of 28
CK
(1 CLKIN cycle). To avoid erroneous grants, HBG should be
ADSST-SHARC-Mel-100