adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet

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adsst-sharc-mel-100

Manufacturer Part Number
adsst-sharc-mel-100
Description
Sharc Mel-100 Audio Processor
Manufacturer
Analog Devices, Inc.
Datasheet
SUMMARY
High performance 32-bit audio processor
Super Harvard Architecture Computer (SHARC)
4 independent buses for dual data, instruction, and
nonintrusive, zero-overhead I/O fetch on a single cycle
Code compatible with all other SHARC family DSPs
Single-instruction-multiple-data (SIMD) computational
architecture—two 32-bit IEEE floating-point computa-
tion units, each with a multiplier, ALU, shifter, and
register file
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
MULT
CONNECT
8 × 4 × 32
DAG1
BUS
(PX)
16 × 40-BIT
REGISTER
8 × 4 × 32
DATA
(PEX)
FILE
DAG2
CORE PROCESSOR
DM ADDRESS BUS
PM ADDRESS BUS
PM DATA BUS
DM DATA BUS
ALU
SHIFTER
BARREL
TIMER
SEQUENCER
PROGRAM
INSTRUCTION
32 × 48-BIT
CACHE
32
32
64
64
Figure 1. Functional Block Diagram
SHIFTER
BARREL
ALU
ADDR
PROCESSOR PORT
REGISTER
16 × 40-BIT
ADDR
DATA
(PEY)
FILE
DUAL-PORTED BLOCKS
Serial ports offer I
simultaneous receive or transmit pins, which support up
to 16 transmit or 16 receive channels of audio
Integrated peripherals—integrated I/O processor,
0.5 Mbit on-chip SRAM, SDRAM controller, glueless
multiprocessing features, and I/O ports (serial, link,
external bus, SPI®, and JTAG)
SHARC Mel-100 supports 32-bit fixed-point, 32-bit
floating-point, and 40-bit floating-point formats
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
TWO INDEPENDENT
DATA
DUAL-PORTED SRAM
DATA
MULT
ADSST-SHARC-Mel-100
IOD
DATA
64
2
DATA
S support via 8 programmable and
(MEMORY MAPPED)
© 2003 Analog Devices, Inc. All rights reserved.
I/O PORT
DATA BUFFERS
STATUS, AND
REGISTERS
CONTROL,
ADDR
IOP
SHARC
ADDR
Audio Processor
IOA
18
I/O PROCESSOR
MULTIPROCESSOR
SERIAL PORTS (4)
LINK PORTS (2)
®
SPI PORTS (1)
CONTROLLER
EXTERNAL PORT
TEST & EMULATION
INTERFACE
HOST PORT
www.analog.com
CONTROLLER
DMA
Mel-100
ADDR BUS
DATA BUS
FLAGS
SDRAM
JTAG
GPIO
MUX
MUX
12
24
32
16
20
6
8
5
4

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