kfm2g16q2a-deb8 Samsung Semiconductor, Inc., kfm2g16q2a-deb8 Datasheet - Page 92

• Manufacturer Part Number: kfm2g16q2a-deb8
• Description: 2gb Muxonenand A-die
• Manufacturer: Samsung Semiconductor, Inc.

3.5 Data Protection During Power Down Operation
The device is designed to offer protection from any involuntary program/erase during power-transitions.
RP pin which provides hardware protection is recommended to be kept at VIL before Vcc drops to 1.5V.
3.6 Load Operation
The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in order to ini-
tiate the load.
During a Load operation, the device:
Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read from the
BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation can be checked
by the host if required.
The device has a dual data buffer memory architecture (DataRAM0, DataRAM1), each 2KB in size. Each DataRAM buffer has 4
Sectors. The device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to the
other data buffer. Refer to the information for more details in section 3.15.1, "Read-While-Load Operation".
Load Operation Flow Chart Diagram
MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
-Transfers the data from NAND Flash array into the BufferRAM
-ECC is checked and any detected and corrected error is reported in the status response as well as
any unrecoverable error.
Write ‘BSA, BSC’ of DataRAM
Write 0 to interrupt register
Add: F200h DQ=BSA, BSC
Write ‘DFS*, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Add: F107h DQ=FPA, FSA
Write ‘FPA, FSA’ of Flash
Select DataRAM for DDP
Add: F241h DQ=0000h
See Timing Diagram 6.21
See Timing Diagrams 6.11
Add: F101h DQ=DBS
NOTE 1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
Start
1)
Add: F240h DQ[10]=Error
Add: F241h DQ[15]=INT
Write ‘Load’ Command
low to high transition
Host reads data from
Wait for INT register
DQ=0000h or 0013h
Read completed
Read Controller
Status Register
Add: F220h
DQ[10]=0?
DataRAM
- 92 -
YES
NO
* DBS, DFS is for DDP
Map Out
FLASH MEMORY