lrs1329 Sharp Microelectronics of the Americas, lrs1329 Datasheet
lrs1329
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lrs1329 Summary of contents
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... RELIMINARY RODUCT PECIFICATIONS LRS1329 Stacked Chip 16M Flash and 2M SRAM ® (Model No.: LRS1329) Spec No.: MFM2-J11601 Issue Date: June 10, 1999 Integrated Circuits Group ...
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... Communications *Control equipment -Medical equipment (4) Please direct all queries above three Paragraphs l Please direct all queries regarding representative of the company. LRS1329 for it contains material protected full or in part,. of this material of the company. herein, please observe.the conditions in the following paragraphs event shall ...
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... Flash 8. Absolute Maximum Ratings 9. Recommended DC Operating Conditions 10. pi* Capacitance . - . . . . . ‘ 11. DC Electrical Characteristics 12. AC Electrical Characteristics 13. AC Electrical Characteristic’s 14. Data Retention Characteristics 15. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17. Design Consideration . . . . . . . . . . . . , . . . . . . . . . . . . LRS1329 Contents - * - - * - * - - - - - * - - - - Memory . . . . . . . . . . . . . . . (Flash Memory (SRAM for SRM * - * - * - - - * - - - * - - - ...
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... Word/Byte write Suspend Block Erase Suspend to Nerd/Byte Block Erase Suspend to Read SRAM OAccess Time OOperat ing current OStandby current OData retention current LRS1329 Part 1 Overview memory organized as lMx16/2M static RAM in one package 2 -25 hardened ) plastic package and SRAM has P-type bulk ...
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... Write, Erase Power Supply (Flash) F-V,, Block Erase and Word/Byte Write : F-V,,=V,,, : Al 1 Blocks Locked 1 F-V,,<Vppll( F-GND GND (Flash) GND (SRAM) S-GND No Connect Test pins (Should be open) LRS1329 (Flash) m, Erase/Write can operate to all block) x8 mode: VIL, x16 mode: VI, V,, (Flash) ; Not used in x8 mode. 3 ...
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... F-s *5. F-A., set to V,, or VI, in byte mode (F-BYTE=Vn). *6. F-‘RP set to V,, or V,, . *7. See the following SRAM Standby mode. Block Diagram .F-?i? i F-X F-E :’ F :> F-BYTE :T S-A S-E, I s-c> j S-OE ; S-IRE LRS1329 F-B F-3 F-E S-CE, S-GE, S ’ ’ Characteristics. ...
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... See the Following Identifier *5. See the following Write Protection Operation F-V,, F- Block Erase V or “t Word/Byte Write >V LRS1329 4OH t,e WA 10H *5 XA Boll Write XA DOH *5 Write by SHARP for not be used. ’ Truth Table. the device. being erased written. ...
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... WORD/BYTE WRITE SUSPENDED STATUS (WBWSS) 1 =Word/ByteWrite Suspended 0 =Word/ByteWrite in Progress/Completed DEVICE PROTECT STATUS ( F-‘WP or F-@’ Lock Detected, Operation Abort 0 = Unlock RESERVED FOR FUTURE ENBANCEMENTS LRS1329 WBWS VPPS WBWSS NOTES : Check RYm or SR.7 to determine word/byte write completion. whi 1 e SR. 7=“ ...
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... SHARP Memory Map for Flash Memory Address [A,.-hl 4K*word/8K-byte 4K-word/BK-byte 4K-word/BK-byte I ~~~ ..... MSB Mode X8 LRS1329 Parameter Block Block Parameter Parameter Block 32K-word/64K-byte Main Block 32X-word/64K-byte Main Block 323.word/64K-byte Main Block 32K-word/64K-byte Main Block 32K-word/64K.byte Main Block 32K-word/64K-byte ...
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... IL v, (*3) Notes) * the lower one of S-V,, and F-V, _ *2. -2.OV undershoot is allowed *3. This voltage is applicable 10. Pin Capacitance Parameter Symbo 1 Input capacitance Crw I/O capac i tance C I/o Note) *1 Sampled but not 100% Jested LRS1329 Ratings Symbo 1 -0 -0.2 (*4) to vcc+o.3 IN -25 to +85 T OPT to +125 -65 T, -0.2 (*4) to +14.0(*5) F- ...
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... VP, St andby or T-V PI Read Current V, Deep Power-Down Current fpp Word/Byte Write Curren Block Erase ‘Current VP, I,, Word/Byte Write or slack Erase Suspend Zurrent Standby Current S-V, Operation Current LRS1329 istics (T.= -25 “r: to +85 Symbo 1 Conditions I =V, or CND V,, LX VOIR =V, or GND Ll F-E=F-3=F-V, fO.2V bcs F--%F-V, fO.2V (*2,7) or F-CNDfO ...
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... V, fO.2V 5. Block erases and word/byte in the range between V,, (max) and V,, (min), 6. F-3 connection supply 7. F-m is V&O.2V in word mode and is CWO.2V F-@ is V&O.ZV or CNDztO. 2V. LRS1329 -25’c to +ss”c and T,=+25”C. typical or GNMO.2V. TTL inputs are either writes are inhibited when F-V,, SV,,, and above V,, (max) ...
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... Recovery before Read F-V,, Hold from Valid SRD, F-RY/BTHigh F-E V,,,, Hold from Valid SRD, F-RY/k@-High F-w Vi, Hold from Valid SRD, F-RY/B?High F-BYTE Setup to F-E Going High F-BYTE Hold from F% Hinh 1 LRS1329 2 1.35 V lTTLfc, (30pF) -25°C to +SS”c CT,= the falling edge of F-OEwithout (T,= -25°C to +85” ...
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... SHARP Write Cycle (F-z Control led) (*2) Notes) *2. Read timing characteristics same as during read-only *3. Refer to Section 5. Flash erase or word/byte write. LRS1329 (T,= -25°C to +85X during block erase and word/byte operations. Refer to AC Characteristics Memory Command Definition for valid 12 ) V,F 2.7v to 3.6v) write operations are th for Read Cycle. ...
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... Erase and Word/Byte Write Performance 32K-word hHav2 Block Erase t 64K-byte MPVZ Time 4K-word 8K-byte huur Word/ByteWrite Suspend Latency Time to Read hnRz1 hm3z2 Erase Suspend Latency Time to Read hlmz2 LRS1329 (T,= -25°C to +85 c, V Block 1.2 Block Block 0.5 Block 7.5 8.6 19.3 23 --. P’s ...
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... Flash Memory AC Characteristic Timing Chart Read Cycle timing chart Address Address HIGH Z DQ F-V, F-BYTE timing Waveform Device Standby Address Address m F-BYTE )ATA (D/Q> HIGH Z (IQ,-W> t AVPV c DATA @/Cl) HIGH Z LRS1329 Device Data Valid Selection Address Stable L Data Valid Selection Address Stable HIGH Z ...
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... F-i@ ( F-V,, Notes: *l. V,, Power -up and standby. *2. Write block erase or word/byte *3. Write block erase confirm or valid *4. Automated erase or program delay. *5. Read status register data. *6. Write Read Array command. LRS1329 controlled himlII> ~Wvll > tjt write setup. address and data b.L \ hWH ...
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... SHARP Write cycle timing chart (F-E controlled) *1 l-V--% Address F-E F-Z F-E w F-BYTE F-RY/BY Notes: *l. V,, Power-up and standby. *2. Write block erase or word/byte *3. Write block erase confirm or valid *4. Automated erase or program delay. *5. Read status register data Read Array command. Wri LRS1329 A write setup. address and data. 16 ...
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... AC High Z FRY/BY @) voL V III F -@ ( High Z F-RY/BY( III F-B ( F-i@(P) LRS1329 (T,= -25 ‘c to +85 ‘c , Min. SW. true 100 is not hz 100 h complete with loons. from the later of F-RY/BY going High Z of F-3 low minimum 1oOns is required there t,m (A)Reset During Read Array Mode tpu.2 I- > ...
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... Chip enable access time(S-E) (s-c&J Write Cycle S-z High to output active S-B Low to output in High impedance L *2. Active output to High impedance and High impedance to output specified for a f20OmV transition LRS1329 0 2 1.5 V llTLtC, (30pF) (*l) capacitance. , v,= 2.7Vto3 +85 ‘c Sym. Min. Max ...
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... SHARP SRAM AC Charaterestics Timing Chart Read cycle timing chart- (*3) Address s -CE, S-C& S-X D OOI *3 S%? is high for Read cycle. Write cycle timing chart- (S-E Controlled) < Jf Address S-OE S-CE, S-CE, t (*I < \\\\\\\\\\\\\\ D OUT D IN LRS1329 tic ’ I OIL? ,, trn /' / (*8) Data Valid \ 19 > ‘( tow > (*lo) km ...
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... If S-E, goes low or S-C& S-WE going low, the outputs *10. If S-XI goes high or S-C& S-E going high, the outputs LRS1329 fixed < (*s) / Data Valid of a low SE,, a high S-C& and a low S-x, transition among S-m going low, S-CE,going ...
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... CDP . CE ___.. _..__ .___ _ _____ _ __._. __________________.........~ _ .__.____.____.______ _ _.____. ___ ________.__._______...................... ._..___._.__......................... Note) *3. To control the data retention S-C& between V,, and Vcc, -0. 0.2V and during LRS1329 (T,= Conditions 2v (*2> LV,,-0.2v (*2) (S-E, control led) or S-C&SO. 2V (S-C& control Data Retention mode . ...
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... The power supply is needed to be designed carefully Flash Memory is in standby mode when the other is active. supplies is necessary between SWAM and Flash Memory. Note peak current of control signals (F-E, S-CE,, S-C&). LRS1329 16M(x8/x16) CSp package that a of the voltage is less than 0.3V. should not be BIGH when F-Eis ...
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... F-s When the F-E is kept low during power up and power down sequence, write the flash memory is disabled, write protecting For the details of F-E control, AC Electrical.Characteristics) LRS1329 the limit specified in the specification on some systems. or power supply may be interpreted unwanted overwriting, write protect against them in the boot block. ...
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... V,,(See 11. DC Characteristics) produce spurious Device operations at invalid Vcc voltage(see results and should not be attempted. LRS1329 ceramic capacitor connected between its V, and GND capacitors should be placed as close as in the target pay attention to the Vr, Power Supply trace. considerations given to the Vcc power bus. “ ...
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INDEX TOP VIEW-,-- ---e TYP TYP TYP 000bOL!000OOO ” 0000~0000 a P oooo;ooo~ m --- 4 0000~0000 .----e- oT~~~j-cc.---- P BOTTOM VIEW OOOOiOOOO ” ...