am49dl3208g Advanced Micro Devices, am49dl3208g Datasheet - Page 5

• Manufacturer Part Number: am49dl3208g
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram 32 Megabit 2 M X 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 8 Mbit 512 K X 16-bit Pseudo Static Ram
• Manufacturer: Advanced Micro Devices

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations. . . . . . . . . . . . . . . . . 9
Flash Device Bus Operations . . . . . . . . . . . . . . . 10
Common Flash Memory Interface (CFI) . . . . . . . 20
Flash Command Definitions . . . . . . . . . . . . . . . . 24
March 12, 2004
Special Package Handling Instructions .................................... 7
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 11
Simultaneous Read/Write Operations with Zero
Latency ................................................................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Sector/Sector Block Protection and Unprotection .................. 16
Write Protect (WP#) ................................................................ 17
Temporary Sector Unprotect .................................................. 17
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 19
Hardware Data Protection ...................................................... 20
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter SecSi™ Sector/Exit SecSi Sector Command
Sequence ............................................................................... 24
Word Program Command Sequence ..................................... 25
Chip Erase Command Sequence ........................................... 26
Sector Erase Command Sequence ........................................ 26
Table 1. Device Bus Operations .....................................................10
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Table 2. Top Boot Sector Addresses ............................................. 12
Table 3. Top Boot SecSi™ Sector Addresses ............................... 14
Table 4. Bottom Boot Sector Addresses ......................................... 14
Table 5. Bottom Boot SecSi™ Sector Addresses .......................... 15
Table 6. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ............................................................. 16
Table 7. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection ........................................... 16
Figure 1. Temporary Sector Unprotect Operation ...........................17
Figure 2. In-System Sector Protect/Unprotect
Algorithms .......................................................................................18
Figure 3. SecSi Sector Protect Verify ..............................................20
Low V
Write Pulse “Glitch” Protection ........................................................20
Logical Inhibit ..................................................................................20
Power-Up Write Inhibit ....................................................................20
Table 8. CFI Query Identification String ..........................................21
Table 9. System Interface String..................................................... 22
Table 10. Device Geometry Definition ............................................22
Table 11. Primary Vendor-Specific Extended Query ......................23
Unlock Bypass Command Sequence ..............................................25
Figure 4. Program Operation ..........................................................26
CC
Write Inhibit .......................................................................20
A D V A N C E
Am49DL3208G
I N F O R M A T I O N
Flash Write Operation Status. . . . . . . . . . . . . . . . 29
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 33
Flash DC Characteristics . . . . . . . . . . . . . . . . . . . 34
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 36
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Pseudo SRAM AC Characteristics . . . . . . . . . . . 51
Erase Suspend/Erase Resume Commands ........................... 27
DQ7: Data# Polling ................................................................. 29
RY/BY#: Ready/Busy# ............................................................ 30
DQ6: Toggle Bit I .................................................................... 30
DQ2: Toggle Bit II ................................................................... 31
Reading Toggle Bits DQ6/DQ2 ............................................... 31
DQ5: Exceeded Timing Limits ................................................ 31
DQ3: Sector Erase Timer ....................................................... 31
CMOS Compatible .................................................................. 34
Pseudo SRAM CE#s Timing ................................................... 39
Read-Only Operations ........................................................... 40
Hardware Reset (RESET#) .................................................... 41
Flash Erase and Program Operations .................................... 42
Temporary Sector Unprotect .................................................. 47
Alternate CE#f Controlled Erase and Program
Operations .............................................................................. 49
Power Up Time ....................................................................... 51
Read Cycle ............................................................................. 51
Figure 5. Erase Operation .............................................................. 27
Table 12. Command Definitions ..................................................... 28
Figure 6. Data# Polling Algorithm .................................................. 29
Figure 7. Toggle Bit Algorithm ........................................................ 30
Table 13. Write Operation Status................................................... 32
Figure 8. Maximum Negative Overshoot Waveform ...................... 33
Figure 9. Maximum Positive Overshoot Waveform ........................ 33
Figure 10. I
Automatic Sleep Currents) ............................................................. 35
Figure 11. Typical I
Figure 12. Standby Current ISB CMOS ......................................... 37
Figure 13. Test Setup .................................................................... 38
Figure 14. Input Waveforms and Measurement
Levels ............................................................................................. 38
Figure 15. Timing Diagram for Alternating
Between Pseudo SRAM and Flash ................................................ 39
Figure 16. Read Operation Timings ............................................... 40
Figure 17. Reset Timings ............................................................... 41
Figure 18. Program Operation Timings .......................................... 43
Figure 19. Accelerated Program Timing Diagram .......................... 43
Figure 20. Chip/Sector Erase Operation Timings .......................... 44
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 45
Figure 22. Data# Polling Timings (During Embedded
Algorithms) ..................................................................................... 45
Figure 23. Toggle Bit Timings (During Embedded
Algorithms) ..................................................................................... 46
Figure 24. DQ2 vs. DQ6 ................................................................. 46
Figure 25. Temporary Sector Unprotect Timing
Diagram .......................................................................................... 47
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 48
Figure 27. Flash Alternate CE#f Controlled Write
(Erase/Program) Operation Timings .............................................. 50
Figure 28. Pseudo SRAM Read Cycle—Address
CC1
Current vs. Time (Showing Active and
CC1
vs. Frequency ............................................ 35
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