am49dl3208g Advanced Micro Devices, am49dl3208g Datasheet - Page 14

• Manufacturer Part Number: am49dl3208g
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram 32 Megabit 2 M X 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 8 Mbit 512 K X 16-bit Pseudo Static Ram
• Manufacturer: Advanced Micro Devices

Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
12
CC5
f in the table represents the automatic sleep mode
Sector
SA10
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA11
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A D V A N C E
Sector Address
SS
000000xxx
000001xxx
000010xxx
000100xxx
000101xxx
001000xxx
001001xxx
001010xxx
010000xxx
010001xxx
010010xxx
000011xxx
000110xxx
000111xxx
001011xxx
001100xxx
001101xxx
001110xxx
±0.3 V, the device
001111xxx
A20–A12
Table 2. Top Boot Sector Addresses
RP
ACC
Am49DL3208G
, the
+
I N F O R M A T I O N
draws CMOS standby current (I
held at V
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
Sector Size
(Kwords)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
READY
IL
but not within V
(during Embedded Algorithms). The
Figure 17
READY
IH
.
for the timing diagram.
IH
SS
058000h–05FFFFh
, output from the device is
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
008000h–0FFFFh
000000h–07FFFh
010000h–17FFFh
Address Range
±0.3 V, the standby cur-
(not during Embedded
CC4
(x16)
f). If RESET# is
March 12, 2004
RH
after the