am49dl3208g Advanced Micro Devices, am49dl3208g Datasheet
am49dl3208g
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am49dl3208g Summary of contents
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Data Sheet September 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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... ADVANCE INFORMATION Am49DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 32 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — Access time as fast Package — ...
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... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Am49DL3208G March 12, 2004 ...
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... Figure 25. Temporary Sector Unprotect Timing Diagram .......................................................................................... 47 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 48 Alternate CE#f Controlled Erase and Program Operations .............................................................................. 49 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings .............................................. 50 Pseudo SRAM AC Characteristics . . . . . . . . . . . 51 Power Up Time ....................................................................... 51 Read Cycle ............................................................................. 51 Figure 28. Pseudo SRAM Read Cycle—Address Am49DL3208G 3 ...
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... Figure 32. Pseudo SRAM Write Cycle—UB#s and LB#s Control ...55 Flash Erase And Programming Performance . . Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 56 Package Pin Capacitance Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 56 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57 TLB069—69–Ball Fine-Pitch Grid Array ............................................................................... 57 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58 Am49DL3208G March 12, 2004 ...
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... Am49DL3208G Flash Memory RY/BY# 64 MBit Flash Memory DQ15/A– s CCQ SS SSQ 8 MBit DQ15/A–1 to Pseudo SRAM Am49DL3208G Pseudo SRAM DQ0 DQ15/A–1 to DQ0 DQ0 5 ...
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... RESET# CONTROL WE# & COMMAND CE# REGISTER WP#/ACC DQ15–DQ0 A20–A0 Mux OE# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 Am49DL3208G DQ15–DQ0 Mux March 12, 2004 ...
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... V ps DQ12 DQ7 DQ11 NC DQ5 DQ14 integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am49DL3208G Flash only A10 NC Pseudo SRAM only Shared C9 A15 E10 F10 A16 ...
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... PSRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 19 A18–A0 A20–A19 CE#f DQ15–DQ0 CE1#ps CE2ps OE# WE# WP#/ACC RESET# UB#ps LB#ps Am49DL3208G RY/BY# March 12, 2004 ...
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... Mbits Order Number Am49DL3208GT70I Am49DL3208GB70I Am49DL3208GT71I Am49DL3208GB71I needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables inputs and control levels they require, and the result- ing output ...
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... WE# should remain at V whether the device outputs array data in words or bytes. . CE#f is the power The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This Am49DL3208G WP#/ACC DQ7– DQ15– (Note 4) DQ0 X ...
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... If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed the table represents the standby current spec- CC3 ification. Am49DL3208G must not be asserted on HH shows how read and write cycles f and the table represent the cur- CC7 ...
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... Am49DL3208G f). If RESET# is CC4 but not within V ±0.3 V, the standby cur- SS (during Embedded Algorithms). The (not during Embedded READY after the Figure 17 for the timing diagram. , output from the device is IH (x16) Address Range 000000h– ...
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... Am49DL3208G (x16) Address Range 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h– ...
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... Am49DL3208G Sector Size (x16) (Words) Address Range 128 1F0000h–1FF07Fh (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h– ...
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... Bottom Boot SecSi™ Sector Addresses Sector Address A20–A12 000000xxx Am49DL3208G (x16) Address Range 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h– ...
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... This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previ- Am49DL3208G Sector/Sector Block A20–A12 Size 111111XXX ...
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... All protected sectors unprotected (If WP#/ACC = V sectors 0 and 1 (bottom boot and 70 (top boot) will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am49DL3208G Table is removed from the RE- ID shows the algorithm, and , sectors 0, 1, 69, and 70 ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am49DL3208G START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Am49DL3208G Figure 2, ex This IH ...
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... For further information, please refer to the CFI Specifi- LKO cation and CFI Publication 100, available via the is World Wide Web at http://www.amd.com/flash/cfi. Al- CC ternatively, contact an AMD representative for copies of these documents. Am49DL3208G or WE initiate a write cycle and OE during power up, IL ...
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... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am49DL3208G Description 21 ...
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... Erase Block Region 3 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h 0000h 0000h Erase Block Region 4 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h Am49DL3208G Description pin present) PP pin present µs µ (00h = not supported) ...
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... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 0085h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 0095h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 000xh 02h = Bottom Boot Device, 03h = Top Boot Device Am49DL3208G Description 23 ...
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... Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Am49DL3208G 2 and 4 show March 12, 2004 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Opera- tions table in the AC Characteristics section for parameters, and Am49DL3208G 12 and 13 show the re- any operation HH Figure 18 for timing diagrams ...
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... The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. Am49DL3208G Figure 20 section for timing dia- 12 and ...
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... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Yes Erasure Completed Notes: 1. See Tables 12 and 13 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 5. Erase Operation Am49DL3208G Embedded Erase algorithm in progress 27 ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am49DL3208G Fourth Fifth Sixth Data Addr ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am49DL3208G Figure 22 Yes Yes PASS 29 ...
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... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm Am49DL3208G Figure 23 in Figure 24 shows the differ- ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits. Am49DL3208G Figure 7). 31 ...
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... The device outputs array data if the system addresses a non-busy bank Table 13. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am49DL3208G DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... Operating ranges define those limits between which the functionality of the device is guaranteed. March 12, 2004 +0.8 V –0.5 V –2 Figure 8. Maximum Negative + –2 2 Maximum DC Figure 9. Maximum Positive Am49DL3208G Overshoot Waveform Overshoot Waveform 33 ...
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... CC CC min I = –100 µ min 4. Automatic sleep mode enables the low power mode when addresses remain stable for t current is 200 nA max Not 100% tested. Am49DL3208G Min Typ Max Unit ±1.0 µA 35 µA 35 µA ±1.0 µA 35 µ ...
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... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note °C March 12, 2004 1500 2000 2500 Time Frequency in MHz Figure 11. Typical I vs. Frequency CC1 Am49DL3208G 3000 3500 4000 3 ...
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... IH IL CE1#s=V , CE2 IL: Other inputs = IL 85° 3 CE1#s=V , CE2 IL: Other inputs = IL 85° 3 ns. Am49DL3208G Min Typ Max –1.0 1.0 –1.0 1 –0.2 0.4 (Note 3) V +0.2 CC 2.2 (Note 2) 0.4 2.2 0 March 12, 2004 Unit µ ...
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... PSEUDO SRAM DC AND OPERATING CHARACTERISTICS (µA) Note: ° for reference only 2. Not 100% tested Sample Size of 5 March 12, 2004 2.7 2 Figure 12. Standby Current ISB CMOS Am49DL3208G 2.9 37 ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am49DL3208G 70, 85 Unit 1 TTL gate 0.0–3 ...
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... Pseudo SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 15. Timing Diagram for Alternating March 12, 2004 — t CCR t CCR Between Pseudo SRAM and Flash Am49DL3208G Test Setup All Speeds Unit Min CCR t CCR 39 ...
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... Test Setup CE# Read Toggle and Data# Polling Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 16. Read Operation Timings Am49DL3208G All Speed Options Unit Min 70 Max 70 IL Max 70 IL Max 30 Max 16 Max 16 Min 0 Min 0 Min 10 /2 ...
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... RESET# March 12, 2004 Description Max Max Min Min Min Min Ready Reset Timings during Embedded Algorithms t Ready t RP Figure 17. Reset Timings Am49DL3208G All Speed Options Unit µs 20 500 ns 500 µ ...
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... Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information CE#f Low During Toggle Read Toggle and Data# Polling Word Am49DL3208G All Speed Options Unit Min 70 ns Min 0 ns Min ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am49DL3208G Read Status Data (last two cycles WHWH1 Status D OUT VHH 43 ...
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... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am49DL3208G Read Status Data WHWH2 In Complete Progress t RB March 12, 2004 ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am49DL3208G Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data 45 ...
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... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am49DL3208G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read March 12, 2004 ...
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... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector Unprotect Timing Diagram March 12, 2004 Min Min Min Min Program or Erase Command Sequence t RSP Am49DL3208G All Speed Options Unit 500 ns 250 ns µs 4 µ ...
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... For sector protect For sector unprotect SADD = Sector Address. Figure 26. Sector/Sector Block Protect and Valid* Valid* Verify 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am49DL3208G Valid* 40h Status March 12, 2004 ...
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... Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. March 12, 2004 Word Am49DL3208G All Speed Options Unit Min 70 ns Min 0 ns Min ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am49DL3208G PA DQ7# D OUT March 12, 2004 ...
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... CE# Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB for continuous periods < 10 µs. RC Am49DL3208G . IH Speed Unit ...
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... CO1 t CO2 OLZ t BLZ t LZ (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ for continuous periods < 10 µs. RC Figure 29. Pseudo SRAM Read Cycle Am49DL3208G OHZ Data Valid March 12, 2004 ...
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... WP (See Note (See Note 3) High-Z t WHZ Data Undefined applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am49DL3208G Speed Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low Am49DL3208G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low Figure 32. Pseudo SRAM Write Cycle— UB#s and LB#s Control Am49DL3208G t (See Note Data Valid ...
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... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT Test Conditions Am49DL3208G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... IN THE OUTER ROW E/2 BALL PITCH 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. SOLDER BALL PLACEMENT 9. NOT USED. DEPOPULATED SOLDER BALLS 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am49DL3208G ...
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... Revision A+2 (March 12, 2004) Connection Diagram Corrected mismarked balls. Table 12. Command Definitions Changed device ID for top boot to 01h and for bottom boot to 00h.. Flash AC Characteristics Removed Word Configuration section and CIOf Tim- ings figures.. Am49DL3208G March 12, 2004 ...
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... Guadalajara - LatinRep/WW Rep Mexico City - LatinRep/WW Rep Monterrey - LatinRep/WW Rep PUERTO RICO, Boqueron - Infitronics ©2003 Advanced Micro Devices, Inc. Am49DL3208G 01/03 Printed in USA 59 ...