s71pl512nd0 Meet Spansion Inc., s71pl512nd0 Datasheet - Page 7

• Manufacturer Part Number: s71pl512nd0
• Description: Two S29pl256n Devices 32 M X 16-bit Cmos 3.0-volt Only Simultaneous Read/write, Page-mode Flash Memory
• Manufacturer: Meet Spansion Inc.

Figures
December 6, 2005 S71PL512ND0_00_A2
Figure 4.1.
Figure 4.2.
Figure 5.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 10.1
Figure 10.2
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Figure 13.10 Accelerated Program Timing Diagram ..................................................................................................63
Figure 13.11 Chip/Sector Erase Operation Timings ...................................................................................................64
Figure 13.12 Back-to-back Read/Write Cycle Timings ...............................................................................................64
Figure 13.13 Data# Polling Timings (During Embedded Algorithms)............................................................................65
Figure 13.14 Toggle Bit Timings (During Embedded Algorithms).................................................................................65
Figure 13.15 DQ2 vs. DQ6 ....................................................................................................................................66
Figure 19.1
Figure 19.2.
Figure 25.1
Figure 27.1
Figure 27.2.
Figure 27.3.
Figure 27.4.
Figure 27.5.
Figure 27.6.
Figure 27.7.
Simultaneous Operation Block Diagram for S29PL256N and S29PL127N ...................................................39
Simultaneous Operation Block Diagram for S29PL129N ..........................................................................40
V
Connection Diagram – 84-ball Fine-Pitch Ball Grid Array .......................................................................... 9
Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array .........................................................................10
Logic Symbols – PL256N, PL129N, and PL127N .....................................................................................12
Single Word Program Operation ..........................................................................................................23
Write Buffer Programming Operation ...................................................................................................26
Sector Erase Operation ......................................................................................................................28
Write Operation Status Flowchart ........................................................................................................35
Advanced Sector Protection/Unprotection .............................................................................................44
Lock Register Program Algorithm.........................................................................................................48
Maximum Negative Overshoot Waveform .............................................................................................55
Maximum Positive Overshoot Waveform...............................................................................................55
Test Setup .......................................................................................................................................56
Input Waveforms and Measurement Levels...........................................................................................57
Read Operation Timings .....................................................................................................................60
Page Read Operation Timings .............................................................................................................61
Reset Timings...................................................................................................................................61
Program Operation Timings ................................................................................................................63
Power Up 1 (CS1# Controlled) ............................................................................................................79
Power Up 2 (CS2 Controlled) ..............................................................................................................79
Output Load .....................................................................................................................................82
Timing Waveform of Read Cycle(1)......................................................................................................83
Timing Waveform of Read Cycle(2)......................................................................................................84
Timing Waveform of Page Cycle (Page Mode Only).................................................................................84
Write Cycle #1 (WE# Controlled) ........................................................................................................85
Write Cycle #2 (CS1# Controlled) .......................................................................................................85
Timing Waveform of Write Cycle(3) (CS2 Controlled) .............................................................................86
Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) .....................................................................86
CC
Power-Up Diagram ......................................................................................................................57
P r e l i m i n a r y
S71PL512ND0 MirrorBit™ Flash Family
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