s71pl512nd0 Meet Spansion Inc., s71pl512nd0 Datasheet - Page 19

• Manufacturer Part Number: s71pl512nd0
• Description: Two S29pl256n Devices 32 M X 16-bit Cmos 3.0-volt Only Simultaneous Read/write, Page-mode Flash Memory
• Manufacturer: Meet Spansion Inc.

9
9.1
November 23, 2005 S29PL-N_M0_A4
Device Operations
Device Operation Table
9.1.1 Dual Chip Enable Device Description and Operation ( PL129N Only)
This section describes the read, program, erase, simultaneous read/write operations, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see
itself does not occupy any addressable memory location. Instead, the command register is com-
posed of latches that store the commands, along with the address and data information needed
to execute the command. The contents of the register serve as input to the internal state machine
and the state machine outputs dictate the function of the device. Writing incorrect address and
data values or writing them in an improper sequence can place the device in an unknown state,
in which case the system must write the reset command to return the device to the reading array
data mode.
The device must be setup appropriately for each operation.
of each control pin for any particular operation.
Legend: L = Logic Low = V
In, D
Note:
0, 1, 68, and 69)
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate pro-
cessors with a limited addressable range. This product operates as two separate devices in a
single package and requires the processor to address half of the memory space with one chip en-
able and the remaining memory space with a second chip enable. For more details on the
addressing features of the Dual CE# device refer to
and Memory Address Map.
Dual chip enable products must be setup appropriately for each operation. To place the device
into the active state either CE1# or CE2# must be set to V
both CE1# and CE2# must be set to V
pin for any particular operation.
Read
Write
Standby
Output Disable
Reset
IN
Operation
WP# / ACC must be high when writing to upper two and lower two sectors (PL256N: 0, 1,132, and 133; PL127/129N:
= Data In, D
OUT
= Data Out
P r e l i m i n a r y
CE#
IL
H
X
L
L
L
, H = Logic High = V
S29PL-N MirrorBit™ Flash Family
OE#
H
H
L
X
X
Table 9.1 Device Operation
WE#
H
X
H
X
L
IH
IH
, V
.
HH
RESET#
Table 9.2
= 8.5 – 9.5 V, X = Don’t Care, SA = Sector Address, A
H
H
H
H
L
Table 15.1
describes the required state of each control
Table 8.3 on page 16
(See
WP#/ACC
X
X
X
X
X
IL
and
Note)
. To place the device in standby mode,
Table 9.1
Table
(A
15.2). The command register
Addresses
describes the required state
max
A
A
A
A
A
IN
IN
IN
IN
IN
– A0)
for the PL129N Sector
DQ15 – DQ0
High-Z
High-Z
High-Z
D
IN
D
OUT
IN
= Address
17