am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 70

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

SUPERNET 3 Programmable Registers (continued)
70
AMD
Mnemonic
Register
“swpxa0”
“swpxa1”
“swpxa2”
“tmsync”
“wpxa0”
“wpxa1”
“wpxa2”
“swpxs”
“swpr1”
“mod2”
“frmthr”
“earv1”
“wpxsf”
“rpxa0”
“rpxa1”
“rpxa2”
“marw”
“tsync”
“eaa0”
“eaa1”
“eaa2”
“wpxs”
“mdru”
“eacb”
“sabc”
“rpxsf”
“wpr1”
“marr”
“rpxs”
“mdrl”
“sacl”
“rpr1”
“pri1”
“pri2”
“eas”
NPADDR7–0
“1d”
“1e”
“20”
“21”
“22”
“23”
“24”
“25”
“26”
“27”
“28”
“29”
“2a”
“2b”
“2d”
“2e”
“30”
“31”
“32”
“33”
“34”
“35”
“36”
“37”
“38”
“39”
“3a”
“3b”
“3c”
“3d”
“3e”
“40”
“1f”
“2f”
“3f”
Description
Priority register for ASYNC1
Reserved
TSYNC register
Mode register 2
Frame threshold register
End Address of Claim/Beacon area
End Address of receive queue
End Address of synchronous queue
End Address of asynchronous queue 0
End Address of asynchronous queue 1
Reserved
Start Address of Claim frame
Start Address of Beacon frame
Write pointer for special frames
Read pointer for special frames
Read Pointer for receive queue
Write pointer for receive queue
Shadow write pointer for receive queue
Write pointer for synchronous queue
Write pointer for asynchronous queue 0
Write pointer for synchronous queue 1
Reserved
Shadow write pointer for synchronous queue
Shadow write pointer for asynchronous queue 0
Shadow write pointer for asynchronous queue 1
Reserved
Read pointer for synchronous queue
Read pointer for asynchronous queue 0
Read pointer for asynchronous queue 1
Reserved
Memory read address register
Memory write address register
Upper 16 bits of memory data register
Lower 16 bits of memory data register
TMSYNC register
P R E L I M I N A R Y
SUPERNET 3