am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 34
am79c850
Manufacturer Part Number
am79c850
Description
Supernet-r 3
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C850.pdf
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Changes and Enhancements to PHY
Changes from SUPERNET 2 PLC
Addition of Scrambler/Descrambler
Scrambler/descrambler is implemented. Scrambling/
descrambling can be disabled either through a pin or
through bit 0 in the PLC_CNTRL_C register.
ENCOFF pin function changed
The function of this pin has changed slightly. In addition
to turning off the Encoder (as in SUPERNET 2 PLC), this
pin, when asserted, now also turns off the Decoder.
34
AMD
PDTR: Phy Data Transmit and Receive Functions
PDTR: Phy Data Transmit and Receive Functions
MAC
MAC
Rx
Tx
Rx
Tx
X9:0
X9:0
Figure 8. WRAP_S or SAS Configuration
RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL
RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL
R9:0
R9:0
Figure 7. WRAP_B Configuration
SUPERNET 3
SUPERNET 3
DAS/SAS Selection Mux
P R E L I M I N A R Y
SUPERNET 3
PHY B
BIST enhanced
The Built-In Self Test (BIST) test now covers part of the
Elasticity Buffer and Framer logic.
Revision Identification
In
PLC_STATUS_A register will indicate 01111 on a read
operation. The Revision ID for SUPERNET 2 PLC-S
is 11111.
PHY A
PHY A
SUPERNET
PDTR
PDTR
3
PHY,
bits
19574A-8
19574A-9
TX+, TX–
TX+, TX–
RX+, RX–
RX+, RX–
15:11
of
the
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