am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 24

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

Non-Tag Mode of Operation No Longer
Supported
The SUPERNET 3 only supports the tag mode of
operation for transmit and receive. The non-tag mode of
operation is no longer supported. All functionality
related to the non-tag mode of operation is removed.
This causes the following changes:
1. Bits [7:4] in status register 1 upper (ST1U), indicating
2. Bits [7:4] in status register 1 lower (ST1L), indicating
3. In Command register 2, the commands ‘Transmit
4. Bit 15 in mode register 2 (MDREG2) indicating
Modified TAG Mode Operation
The SUPERNET 3 will have two modes of host interface
to buffer memory. The two modes are distinct and
independent ways of accessing the buffer memory
depending upon the selection of the TAG mode or
modified TAG mode. In TAG mode the SUPERNET 3
provides the local buffer management, i.e the queue
pointers are maintained by SUPERNET 3. Modified
TAG mode is used when the NON-TAG mode users of
FORMAC+ are redesigning for SUPERNET 3. Loading
24
‘Transmit End of Chain of Frames’ (STECFRM-S,
A0, A1, A2) are now reserved. They shall be read as
zero.
‘Transmit Instruction Full’ (STXINFL-S, A0, A1, A2)
are now reserved. They shall be read as zero.
Synchronous
Asynchronous Queue 0’ [0x02], and ‘Transmit
Asynchronous Queue 2’ [0x08] are now reserved.
These values shall not be decoded to any other
instruction.
Buffer Memory Mode is now decoded differently.
This bit shall be read as one upon reset, indicating
TAG mode of operation. If programmed to zero, the
modified TAG mode of operation will be enabled.
This bit selection applies to both receive queues if
MENDRCV bit is set in mode register 3 (MDREG 3).
AMD
Queue’
[0x01],
‘Transmit
P R E L I M I N A R Y
SUPERNET 3
of transmit frames in modified TAG is identical to TAG
mode. The unloading of received frames is different in
Modified TAG mode of operation. The format of a
receive frame is as shown Figure 1. The first long word
in each frame consists of a 16-bit status word and a
16-bit word that gives the length of the frame in bytes.
The status/length word is followed by the data words.
The location of the first byte in the first long word of data
is defined by the byte boundary bits RXFBB1–0 of mode
register (MDREG 2). At the end of the frames that make
up a receive queue, SUPERNET 3 writes a long word
with all bits as a logic 0, which indicates that there is no
more data in this queue. The only function of this word is
to act as an end delimiter. Note that the MSVALID bit in
bit 31 of the status word at the start of the frame is
always in the logic 1 state. Also, when another frame
follows this queue, it overwrites the end delimiter word
with the receive status word of the new frame. After each
frame has been written into buffer memory, SUPERNET
3 write the status and frame length at the start of each
frame, and places an end-indicator word of all 0’s at the
end of the queue. Once a frame is completely received,
the status bit SRCOMP in status register 2 (ST2U) is
set. If the received frame is aborted, the SUPERNET 3
will write the status word indicating the aborted status
(bit 30) and the length field bits will be all zero. If the
receive queue has an overflow condition during frame
reception, the status register bit indicating SRCVOVR in
status register 2 (ST2U bit 11), is set high and the frame
is aborted. An overflow also sets the MSRABT bit (bit
30) in the receive frame status word of the incomplete
frame. The received frames are unloaded by the host
from the buffer memory by using the host request pins
(HSREQ). The RDATA signal is always in the 0 state
and receive frame threshold (RTHR) is not applicable in
modified TAG mode for asserting the RDATA pin. If dual
receive queue operation is selected (MENDRCV, bit 11
in MDREG 3) then the receive status information would
be indicated in the corresponding status register (ST2U
for RECV1 and ST3U for RECV2).