am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 62

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

ADDRESS FILTER TEST SPECIFICATION
Introduction
The Address Filter (AF) core requires a special set of
test patterns to provide adequate fault coverage. The
mask and data bits of the AF are similar to an SRAM cell
and must be tested with the types of test patterns that
are used to test SRAM’s. The main fault models that are
applied in SRAM testing are the stuck-at fault model, the
transition fault model, and the coupling fault model. The
stuck-at fault model describes the condition where a cell
or line is always 0 or 1 and can’t be changed to the
opposite state. The transition fault model describes the
condition where a cell or line fails to undergo a transition
from 0_1 or from 1_0 when it is written. The coupling
fault model describes the condition where a write to a
cell that causes a transition in that cell, also causes a
transition in another cell. In addition to the test
necessary for the above fault models, the CAM contains
additional personality bits, match logic and a priority
encoder that must also be tested.
The AF core will be tested through the use of built-in self
test (BIST). The patterns that need to be applied to the
SRAM portion of the CAM are algorithmic in nature and
can be easily implemented with BIST. The components
of the AF BIST logic will include a state machine, a
data
address generator.
Test Logic Description
This section provides a description of the AF test logic.
BIST Operation
The BIST feature can be accessed by one of two
methods. The first means of access is a serial mode of
access meant to be used with an IEEE 1149.1 Test
Access Port (TAP) controller. The second means of
access is a parallel mode of access using the node
processor interface. Each means of access is described
further below.
TAP Interface
Access to BIST through the TAP interface is provided so
that the core can be tested in a product that supports the
RUNBIST instruction of the IEEE 1149.1 standard. As
such, the implementation of the BIST should conform to
all the rules described for the RUNBIST instruction in the
standard. Some of these rules apply only to the design
of the TAP controller itself, while others affect the
implementation of the AF BIST logic. The rules that
affect the implementation of the AF BIST logic are
summarized below.
62
AMD
generator,
a
signature
register,
and
P R E L I M I N A R Y
SUPERNET 3
an
The AF will have a serial input and serial output through
which the results of the BIST can be shifted. These
resuls shall be shifted in response to the appropriate
TAP interface signals.
The AF BIST execution will depend on signals provided
by the TAP controller and will run at a rate determined by
the TAP test clock. The clocking of the BIST will be taken
care of external to the AF. This can be done by
multiplexing the normal AF clock with the test clock
during the RUNBIST instruction.
The AF BIST implementation shall not require a seed
value to be serially shifted in.
The minimum number of test clock cycles necessary for
the completion of BIST needs to be provided. After the
minimum number of clock cycles the AF must hold the
results of the BIST constant until requested to shift them
out by the TAP controller.
Each execution of BIST shall provide the same result
and shall not depend on the state of signals received at
non-TAP interface signal.
The serial BIST operation is begun when the tl_bistena
signal from the TAP controller is asserted. This signal
must remain asserted for the minimum duration speci-
fied to guarantee a valid signature. When the minimum
number of clock cycles has passed the tl_bistena signal
will be de-asserted and a short time later the tl_bistse
signal will be asserted to shift out the contents of the
signature register through the af_tdo output. When the
tl_bistena signal becomes de-asserted, the signature
register should hold its content until the tl_bistena signal
is asserted again, or the AF is reset. If the minimum
number of clock cycles for the completion of BIST is not
met, an intermediate signature will be obtained. This
can be used to aid in fault isolation for internal
manufacturing testing.
Node Processor Interface
Access to BIST through the node processor interface is
provided for board and system level testing. BIST is
initiated through this interface by writing the Run BIST
instruction to the AFCMD register. The BISTDONE and
DONE bits in the AFSTAT register are cleared upon
issuing this instruction and the BIST state machine
moves from the idle to the operational state. At the
completion of self test, the BISTDONE and DONE bits
will be set in the AFSTAT register. The DONE bit can be
used to generate an interrupt to the node processor
indicating the completion of the self test. The result of
the self test can be obtained by reading the AFBIST
register and comparing it to the known good signature.