am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 41

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

Built-In Self Test (BIST)
The BIST feature of the SUPERNET 3 is provided to
ease board and system level testing, as well as our own
manufacturing testing. This feature can be accessed
through the TAP as well as the system interface. It is
expected that board level testing will use the TAP
interface, while system level testing will not have access
to the TAP interface and will need to run BIST through
the system interface.
There are two functional units in the SUPERNET 3 that
are tested with BIST. These are the AF CAM core and
the enhanced PHY. The BIST testing of the two
functional units is available through the node processor
interface. See the AF specification for a description of
how to run the BIST for the AF. The enhanced PHY BIST
is run using the PHY BIST access as described in the
SUPERNET 2 PLC data sheet.
BSR Cell No.
Address Filter BIST
Internal PLC BIST
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
SCANBIST
Function
Pin No.
30
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
BIST Signature (hex)
1 5B6B 0553
5B6B
0553
Pin Type
output
output
input
input
input
input
input
input
input
input
input
input
input
input
input
input
P R E L I M I N A R Y
SUPERNET 3
DISCRY function no longer supported
Setting the DISCRY bit in mode register 1 (MDREG1,
bit 6) permitted testing the operation of certain internal
timers such as TRT, THT, TVX, and TMSYNC by
breaking them into smaller segments.
With the enhanced testability features of SUPERNET 3,
the DISCRY function is no longer provided. The bit 6 of
mode register 1 (MDREG1) is reserved and shall return
a value of zero when read.
Summary of Changes to Status and Mode
Registers
The following is the summary of changes. The bits in the
register which are shaded indicate change from
SUPERNET 2. All reserved bits shall be read as zero
except where noted.
Description
npmemack
ready (oecell –1 to force 0, 0 to disable)
r/w
ds
csi
lsclk
npa[7]
npa[6]
npa[5]
npa[4]
npa[3]
npa[2]
npa[1]
npa[0]
npmode
rst
AMD
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