am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 92

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

AC CHARACTERISTICS
Notes:
1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge
2. Tested with C
3. Guaranteed by design—not tested.
4. t DATD is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.
92
Clock and Reset Timing
Internal MENDEC Clock Timing
BIU Timing (Note 1)
11
12
13
14
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
No.
1
2
3
4
5
6
7
9
of SCLK (SCLK ). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK (SCLK ).
vs. Load Chart.
AMD
Parameter
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
tSLVS
tSLVH
tDATD
tDATH
tDTVD
tDTVH
tEOFD
tEOFH
tCSIS
tEOFS
tEOFH
tRDTD
tRDTH
tTDTD
tTDTH
tDATS
tDATIH
tDATE
tDATD
SCLK
SCLKL
SCLKH
SCLKR
SCLKF
RST
BT
X1
X1H
X1L
X1R
X1F
ADDS
ADDH
L
set at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay
SCLK period
SCLK LOW pulse width
SCLK HIGH pulse width
SCLK rise time
SCLK fall time
RESET pulse width
Network Bit Time (BT)
=2*tX1 or tSTDC)
XTAL1 period
XTAL1 HIGH pulse width
XTAL1 LOW pulse width
XTAL1 rise time
XTAL1 fall time
Address valid setup to SCLK
Address valid hold after SCLK
CS or FDS and TC, BE1–0,
R/W setup to SCLK
CS or FDS and TC, BE1–0,
R/W hold after SCLK
Data out valid delay from SCLK
Data out valid hold after SCLK
DTV valid delay from SCLK
DTV valid hold after SCLK
EOF valid delay from SCLK
EOF output valid hold after SCLK
CS inactive prior to SCLK
EOF input valid setup to SCLK
EOF input valid hold after SCLK
RDTREQ valid delay from SCLK
RDTREQ valid hold after SCLK
TDTREQ valid delay from SCLK
TDTREQ valid hold after SCLK
Data in valid setup to SCLK
Data in valid setup after SCLK
Data output enable delay from
SCLK (Note 3)
Data output disable delay from
SCLK (Notes 3, 4)
Parameter Description
Am79C940
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
Test Conditions
Min (ns)
0.4*tSCLK
0.4*tSCLK
15*tSCLK
49.995
40
99
20
20
9
2
9
2
6
6
6
9
9
2
6
6
9
2
0
Max (ns)
0.6*tSCLK
0.6*tSCLK
50.005
1000
101
32
32
32
32
32
25
5
5
5
5