am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 29

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

FUNCTIONAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip
embodies the Media Access Control (MAC) and Physi-
cal Signaling (PLS) sub-layers of the 802.3 Standard.
The MACE device provides the IEEE defined Attach-
ment Unit Interface (AUI) for coupling to remote Media
Attachment Units (MAUs) or on-board transceivers.
The MACE device also provides a Digital Attachment In-
terface (DAI), by-passing the differential AUI interface.
The system interface provides a fundamental data con-
duit to and from an 802.3 network. The MACE device in
conjunction with a user defined DMA engine, provides
an 802.3 interface tailored to a specific application.
In addition, the MACE device can be combined with
similarly architected peripheral devices and a multi-
channel DMA controller, thereby providing the system
with access to multiple peripheral devices with a single
master interface to memory.
Network Interfaces
The MACE device can be connected to an 802.3 net-
work using any one of the AUI, 10 BASE-T, DAI and
GPSI network interfaces. The Attachment Unit Inter-
face (AUI) provides an IEEE compliant differential inter-
face to a remote MAU or an on-board transceiver. An
integrated 10BASE-T MAU provides a direct interface
for twisted pair Ethernet networks. The DAI port can
connect to local transceiver devices for 10BASE2,
10BASE-T or 10BASE-F connections. A General Pur-
pose Serial Interface (GPSI) is supported, which effec-
tively
encoder/decoder, and allows direct access to/from the
integral 802.3 Media Access Controller (MAC) to pro-
vide support for external encoding/decoding schemes.
The interface in use is determined by the PORTSEL
[1–0] bits in the PLS Configuration Control register.
The EADI port does not provide network connectivity,
but allows an optional external circuit to assist in receive
packet accept/reject.
System Interface
The MACE device is a slave register based peripheral.
All transfers to and from the device, including data, are
performed using simple memory or I/O read and write
commands. Access to all registers, including the Trans-
mit and Receive FIFOs, are performed with identical
read or write timing. All information on the system inter-
face is synchronous to the system clock (SCLK), which
allows simple external logic to be designed to interro-
gate the device status and control the network data flow.
The Receive and Transmit FIFOs can be read or written
by driving the appropriate address lines and asserting
CS and R/W. An alternative FIFO access mechanism al-
lows the use of the FDS and the R/W lines, ignoring the
address lines (ADD
conjunction with the FDS input determines whether the
bypasses
4–0
the
). The state of the R/W line in
integrated
Manchester
Am79C940
Receive FIFO is read (R/W high) or the Transmit FIFO
written (R/W low). The MACE device system interface
permits interleaved transmit and receive bus transfers,
allowing the Transmit FIFO to be filled ( primed ) while a
frame is being received from the network and/or read
from the Receive FIFO.
In receive operation, the MACE device asserts Receive
Data Transfer Request (RDTREQ) when the FIFO con-
tains adequate data. For the first indication of a new re-
ceive frame, 64 bytes must be received, assuming
normal operation. Once the initial 64 byte threshold has
been reached, RDTREQ assertion and de-assertion is
dependent on the programming of the Receive FIFO
Watermark (RCVFW bits in the BIU Configuration Con-
trol register). The RDTREQ can be programmed to acti-
vate when there are 16, 32 or 64 bytes of data available
in the Receive FIFO. Enable Receive (ENRCV bit in
MAC Configuration Control register) must be set to as-
sert RDTREQ. If the Runt Packet Accept feature is in-
voked (RPA bit in User Test Register), RDTREQ will be
asserted for receive frames of less than 64 bytes on the
basis of internal and/or external address match only.
When RPA is set, RDTREQ will be asserted when the
entire frame has been received or when the initial 64
byte threshold has been exceeded. See the FIFO Sub-
Systems section for further details.
Note that the Receive FIFO may not contain 64 data
bytes at the time RDTREQ is asserted, if the automatic
pad stripping feature has been enabled (ASTRP RCV
bit in the Receive Frame Control register) and a mini-
mum length packet with pad is received. The MACE de-
vice will check for the minimum received length from the
network, strip the pad characters, and pass only the
data frame through the Receive FIFO.
If the Low Latency Receive feature is enabled (LLRCV
bit set in Receive Frame Control Register), RDTREQ
will be asserted once a low watermark threshold has
been reached (12 bytes plus some additional synchroni-
zation time). Note that the system interface will there-
fore be exposed to potential disruption of the receive
frame due to a network condition (see the FIFO Sub-
System description for additional details).
In transmit operation, the MACE device asserts Trans-
mit Data Transfer Request (TDTREQ) dependent on the
programming of the Transmit FIFO Watermark
(XMTFW bits in the BIU Configuration Control register).
TDTREQ will be permanently asserted when the Trans-
mit FIFO is empty. The TDTREQ can be programmed to
activate when there are 16, 32 or 64 bytes of space
available in the Transmit FIFO. Enable Transmit
(ENXMT bit in MAC Configuration Control register)
must be set to assert TDTREQ. Write cycles to the
Transmit FIFO will not return DTV if ENXMT is disabled,
and no data will be written. The MACE device will com-
mence the preamble sequence once the Transmit Start
Point (XMTSP bits in BIU Configuration Control regis-
ter) threshold is reached in the Transmit FIFO.
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