am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 45

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

General Purpose Serial Interface (GPSI)
The GPSI port provides the signals necessary to pre-
sent an interface consistent with the non encoded data
functions observed to/from a LAN controller such as the
Am7990 Local Area Network Controller for Ethernet
(LANCE). The actual GPSI pins are functionally identi-
cal to some of the pins from the DAI and the EADI ports,
the GPSI replicates this type of interface.
The GPSI allows use of an external Manchester en-
coder/decoder, such as the Am7992B Serial Interface
Adapter (SIA). In addition, it allows the MACE device to
be used as a MAC sublayer engine in a repeater based
on the Am79C980 Integrated Multiport Repeater (IMR).
Simple connection to the IMR Expansion Bus allows the
MAC to view all packet data passing through a number
of interconnected IMRs, allowing statistics and network
management information to be collected.
The GPSI functional pins are duplicated as follows:
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board level continuity test and diag-
nostics. All digital input, output and input/output and in-
put/output pins are tested. Analog pins, including the
AUI differential driver (DO ) and receivers DI , CI ),
and the crystal input (XTAL1/XTAL2) pins, are not
tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the MACE de-
vice. For additional details, consult the IEEE Standard
Test Access Port and Boundary-Scan Architecture
document (IEEE Std 1149.1–1990).
Function
Receive Data
Receive Clock
Receive Carrier Sense
Collision
Transmit Data
Transmit Clock
Transmit Enable
PROM
1
0
0
0
0
Pin Configuration for GPSI Function
M/R
X
0
0
1
1
Type
EAM/R
O
O
I
I
I
I
I
H
H
X
Internal/External Address Recognition Capabilities
LANCE
RENA
RCLK
CLSN
TENA
TCK
No timing requirements
No timing requirements
Low for 200 ns within 512-bits after SFD
No timing requirements
Low for 200 ns within 8-bits after DA field
RX
Pin
TX
SRDCLK
TXDAT+
STDCLK
RXCRS
RXDAT
CLSN
TXEN
Required Timing
MACE
Pin
Am79C940
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO ), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array and a power on
reset circuit. Internal pull-up resistors are provided for
the TCK, TDI and TMS pins.
The TAP engine is a 16 state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. An
independent power on reset circuit is provided to ensure
the FSM is in the TEST_LOGIC_RESET state at
power up.
In addition to the minimum IEEE 1149.1 instruction re-
quirements (EXTEST, SAMPLE and BYPASS), three
additional instructions (IDCODE, TRI_ST and SET_I/O)
are provided to further ease board level testing. All
unused instruction codes are reserved.
After hardware or software reset, the IDCODE instruc-
tion is always invoked. The decoding logic provides sig-
nals to control the data flow in the DATA registers
according to the current instruction.
Each Boundary Scan Register (BSR) cell also has two
stages. A flip-flop and a latch are used in the SERIAL
SHIFT STAGE and the PARALLEL OUTPUT STAGE
respectively.
There are four possible operational modes in the BSR
cell:
(1) CAPTURE
(2) SHIFT
(3) UPDATE
(4) SYSTEM FUNCTION
EXTEST External Test
ID Code ID Code Inspection
Sample
TRI_ST
SET_I/0 Control Boundary To I/0
Bypass
Name
Inst
IEEE 1149.1 Supported Instruction Summary
Sample Boundary
Force Tristate
Bypass Scan
Description
All Received Frames
All Received Frames
Physical/Logical/Broadcast Matches
Physical/Logical/Broadcast Matches
All Received Frames
Received Messages
Data Reg
Selected
BSR
ID Reg
BSR
Bypass
Bypass
Bypass
Test
Normal
Normal
Normal
Test
Normal
Mode
Reg
AMD
Code
0000
0001
0010
0011
0100
1111
Inst
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