am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 65

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Bit 5-4
Bit 3
RCVFW [1–0]
RCVFW
[1–0]
XMTFWU
00
01
10
11
Receive FIFO Watermarks
threshold is reached. When us-
ing the burst mode, TDTREQ will
not be de-asserted until only a
single write cycle can be per-
formed. See the FIFO Sub-sys-
tem section for additional details.
Receive
RCVFW
RDTREQ is asserted in relation
to the number of bytes available
in the RCVFIFO. RCVFW speci-
fies the number of bytes which
must be present (once the packet
has been verified as a non-runt),
before the RDTREQ is asserted.
Note however that in order for
RDTREQ to be activated for a
new frame, at least 64-bytes
must have been received. This
effectively avoids reacting to re-
ceive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature (RPA in
Receive Frame Control) is en-
abled, the RDTREQ pin will be
activated as soon as either
64-bytes are received, or a com-
plete valid receive frame is de-
tected (regardless of length).
RCVFW is set to a value of 10 (64
bytes) after hardware or software
reset.
The RCVFW value will only be
updated when the RCVFWU bit
is set.
Transmit FIFO Watermark Up-
date. Allows update of the Trans-
mit FIFO Watermark bits. The
XMTFW can be written at any
point, and will be read back as
written. However, the new value
in the XMTFW bits will be ignored
until XMTFWU is set (or the
transmit path is reset due to a
controls
FIFO
Bytes
XX
16
32
64
Watermark.
the
point
Am79C940
Bit 2
Bit 1
RCVFWU
XMTBRST Transmit Burst. When set, the
retry failure). The recommended
procedure to change the XMTFW
is to write the new value with
XMTFWU set, in a single write
cycle. The XMTFIFO should be
empty and all transmit activity
complete before attempting a
watermark update, since the
XMTFIFO will be reset to allow
the new pointer values to be
loaded. It is recommended that
the transmitter be disabled by
clearing
XMTFWU will be cleared by the
MACE device after the new
XMTFW value has been loaded,
or by activation of the RESET pin
or SWRST bit.
Receive FIFO Watermark Up-
date. Allows update of the Re-
ceive FIFO Watermark bits. The
RCVFW bits can be written at
any point, and will read back as
written. However, the new value
in the RCVFW bits will be ignored
until RCVFWU is set. The recom-
mended procedure to change the
RCVFW is to write the new value
with RCVFWU set, in a single
write
should be empty before attempt-
ing a watermark update, since
the RCVFIFO will be reset to al-
low the new pointer values to be
loaded. It is recommended that
the receiver be disabled by clear-
ing the ENRCV bit. RCVFWU will
be cleared by the MACE device
after the new RCVFW value has
been loaded, or by activation of
the RESET pin or SWRST bit.
transmit burst mode is selected.
The behavior of the Transmit
FIFO high watermark, and hence
the de-assertion of TDTREQ, will
be modified. TDTREQ will be
deasserted if there are only two
bytes of space available in the
XMTFIFO (so that a full word
write can still occur) or if four
bytes of space exist and the EOF
pin is asserted by the host.
cycle.
the
The
ENXMT
AMD
RCVFIFO
bit.
65