am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 61

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Bit 3–0 RCVCNT
RFS2—Runt Packet Count (RNTPC)
Bit
Bit 7–0 RNTPC
RFS3—Receive Collision Count (RCVCC)
Bit
Bit 7–0 RCVCC
FIFO Frame Count (FIFOFC)
Bit
Bit 7–4 RCVFC
RCVFC[3–0]
RNTPC [7–0]
RCVCC [7–0]
[11:8]
[7–0]
[3–0]
[7–0]
Name
Name
Name
passed to the host. FCS will not
be set if OFLO is set.
The Receive Message Byte
Count indicates the number of
whole bytes in the received mes-
sage from the network. RCVCNT
is 12 bits long, and valid (accu-
rate) only when there are no er-
rors reported in the Receive
Status (RCVSTS). If a late colli-
sion is detected (CLSN set in
RCVSTS), the count is an indica-
tion of the length (in byte times) of
the duration of the receive activ-
ity
RCVCNT [7:0] correspond to bits
7–0 in RFS0 of the Receive
Frame Status. RCVCNT [11–0}
will be invalid when OFLO is set.
Description
The Runt Packet Count indicates
the number of runt packets re-
ceived, addressed to this node,
since the last successfully re-
ceived packet. The value does
not roll over after 255 runt pack-
ets have been detected, and will
remain frozen at the maximum
count.
Description
The Receive Collision Count in-
dicates the number of collisions
detected on the network since
the last successfully received
packet. The value does not roll
over after 255 collisions have
been detected, and will remain
frozen at the maximum count.
Description
Receive Frame Count. The (read
only) count of the frames in the
Receive FIFO. A frame is
counted when the last byte is put
in the FIFO. The counter is
decremented when the last byte
of the frame is read. If the
including
XMTFC[3–0]
(REG ADDR 7)
the
collision.
Am79C940
Bit 3–0 XMTFC
Interrupt Register (IR)
All status bits are set upon occurrence of an event and
cleared when read. The resister is read only. In addition
all status bits are cleared by hardware or software reset.
Bit assignments for the register are as follows:
Bit
Bit 7
Bit 6
JAB
BABL
[3–0]
JAB
BABL
Name
CERR RCVCCO RNTPCO
RCVFC reaches its maximum
value of 15, additional receive
frames will be ignored, and the
Missed Packet Count (MPC) reg-
ister will be incremented for
frames which match the internal
address(es) of the MACE device.
Transmit Frame Count. The
(read only) count of the frames in
the Transmit FIFO. A frame is
counted when the last byte is put
in the FIFO. The counter is
decremented when XMTSV (in
the Transmit Frame Status and
Poll Register) is set and the
Transmit Frame Status read ac-
cess is performed.
Description
Jabber Error. JAB indicates that
the MACE device attempted to
transmit for an excessive time
period (20–150 ms), when using
either the DAI port or the
10BASE-T port. If the internal
jabber timer expires during trans-
mission, the transmit bit stream
will be interrupted, until the inter-
nal transmission ceases and the
unjab timer (0.5 s 0.25 s) ex-
pires. The jabber function will be
disabled, and JAB will not be
set, regardless of transmission
length, when either the AUI or
GPSI ports have been selected.
JAB is READ/CLEAR only, and is
set by the MACE device and re-
set when read. Writing has no ef-
fect. It is also cleared by
activation of the RESET pin or
SWRST bit.
Babble Error. BABL is the trans-
mitter time-out error. It indicates
that the transmitter has been on
the channel longer than the time
required to send the maximum
packet. It will be set after 1519
bytes (or greater) have been
transmitted. The MACE device
will continue to transmit until the
current packet transmission is
over. The INTR pin will be acti-
MPCO
(REG ADDR 8)
RCVINT
AMD
XMTINT
61