am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 79

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Programmer’s Register Model (continued)
SYSTEM APPLICATIONS
Host System Examples
Motherboard DMA Controller
The block diagram shows the MACE device interfacing
to a 8237 type DMA controller. Two external latches are
used to provide a 24 bit address capability. The first
latch stores the address bits A [15:8], which the 8237 will
output on the data line DB [7:0], while the signal ADSTB
is active. The second latch is used as a page register. It
extends the addressing capability of the 8237 from
16-bit to 24-bit. This latch must be programmed by the
system using an I/0 command to generate the signal
LATCHHIGHADR.
The MACE device uses two of the four DMA channels.
One is dedicated to fill the Transmit FIFO and the other
to empty the Receive FIFO. Both DMA channels should
be programmed in the following mode:
Note:
This is the same configuration as used in the IBM PC.
Addr
30
31
Mnemonic
Command Register:
—
—
Memory to memory disabled
DREQ sense active high
DACK sense active low
Normal timing
Late Write
Reserved
Reserved
Am79C940
Contents
The 8237 and the MACE device run synchronous to the
same SCLK. The 8237 is programmed to execute a
transfer in three clock cycles This requires an extra wait
state in the MACE device during FIFO accesses. A sys-
tem not using the same configuration as in the IBM PC
can minimize the bus bandwidth required by the MACE
device by programming the DMA controller in the com-
pressed timing mode.
Care must be taken with respect to the number of trans-
fers within a burst. The 8237 will drive the signal EOP
low every time the internal counter reaches the zero.
The MACE device however only expects EOF asserted
on the last byte/word of a packet. This means, that the
word counter of the 8237 should be initially loaded with
the number of bytes/words in the whole packet. If the ap-
plication requires that the packet will be constructed
from several buffers at transmit time, some extra logic is
required to suppress the assertion of EOF at the end of
all but the last buffer transferred by the DMA controller.
Also note that the DMA controller can only handle either
bytes or words at any time. It requires special handling if
a packet is transferred to the MACE device Transmit
FIFO in word quantities and it ends in an odd byte.
The 8237 requires an extra clock cycle to update the ex-
ternal address latch every 256 transfer cycles. This ex-
ample assumes that an update of the external address
latch occurs only at the beginning of the block transfer.
AMD
R/W
R/W
as 0
R/W
as 0
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